Quad, 14-bit, 50 MSPS
Serial LVDS 1.8 V A/D Converter
AD9259
FUNCTIONAL BLOCK DIAGRAM
FEATURES
AVDD
PDWN
AD9259
T/H
Four ADCs integrated into 1 package
98 mW ADC power per channel at 50 MSPS
SNR = 73 dB (to Nyquist)
DRVDD
DRGND
14
VIN + A
VIN – A
SERIAL
LVDS
D + A
D – A
PIPELINE
ADC
ENOB = 12 bits
SFDR = 84 dBc (to Nyquist)
Excellent linearity
DNL = 0.5 LSB (typical)
INL = 1.5 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power reduced signal option, IEEE 1596.3 similar
Data and frame clock outputs
315 MHz full power analog bandwidth
2 V p-p input voltage range
14
14
VIN + B
VIN – B
PIPELINE
ADC
SERIAL
LVDS
D + B
D – B
T/H
T/H
T/H
VIN + C
VIN – C
SERIAL
LVDS
D + C
D – C
PIPELINE
ADC
14
VIN + D
VIN – D
SERIAL
LVDS
D + D
D – D
PIPELINE
ADC
VREF
FCO+
FCO–
SENSE
+
0.5V
–
DATA RATE
REFT
REFB
REF
SELECT
MULTIPLIER
1.8 V supply operation
Serial port control
SERIAL PORT
INTERFACE
DCO+
DCO–
Full-chip and individual-channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
SCLK/DTP
RBIASAGND CSB SDIO/ODM
CLK+ CLK–
Figure 1.
capturing data on the output and a frame clock (FCO) for
signaling a new output byte are provided. Individual channel
power-down is supported and typically consumes 2 mW when
all channels are disabled.
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam forming systems
Quadrature radio receivers
Diversity radio receivers
Tape drives
Optical networking
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user-
defined test patterns entered via the serial port interface (SPI®).
Test equipment
The AD9259 is available in a Pb-free, 48-lead LFCSP package. It is
specified over the industrial temperature range of −40°C to +85°C.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9259 is a quad, 14-bit, 50 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit that
is designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 50 MSPS and
is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
1. Small Footprint. Four ADCs are contained in a small, space-
saving package; low power of 98 mW/channel at 50 MSPS.
2. Ease of Use. A data clock output (DCO) operates up to
350 MHz and supports double data rate operation (DDR).
3. User Flexibility. Serial port interface (SPI) control offers a wide
range of flexible features to meet specific system requirements.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
4. Pin-Compatible Family. This includes the AD9287 (8-bit),
AD9219 (10-bit), and AD9228 (12-bit).
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock (DCO) for
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
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