Datasheet > AD9259BCPZRL7-50

AD9259BCPZRL7-50

更新时间： 2024-10-28 20:09:07

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
52页	1606K
描述
IC 4-CH 14-BIT FLASH METHOD ADC, SERIAL ACCESS, QCC48, 7 X 7 MM, ROHS COMPLIANT, MO-220VKKD-2, LFCSP-48, Analog to Digital Converter

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AD9259BCPZRL7-50 数据手册

Quad, 14-bit, 50 MSPS

Serial LVDS 1.8 V A/D Converter

AD9259

FUNCTIONAL BLOCK DIAGRAM

FEATURES

AVDD

PDWN

AD9259

T/H

Four ADCs integrated into 1 package

98 mW ADC power per channel at 50 MSPS

SNR = 73 dB (to Nyquist)

DRVDD

DRGND

VIN + A

VIN – A

SERIAL

LVDS

D + A

D – A

PIPELINE

ADC

ENOB = 12 bits

SFDR = 84 dBc (to Nyquist)

Excellent linearity

DNL = 0.5 LSB (typical)

INL = 1.5 LSB (typical)

Serial LVDS (ANSI-644, default)

Low power reduced signal option, IEEE 1596.3 similar

Data and frame clock outputs

315 MHz full power analog bandwidth

2 V p-p input voltage range

VIN + B

VIN – B

PIPELINE

ADC

SERIAL

LVDS

D + B

D – B

T/H

VIN + C

VIN – C

SERIAL

LVDS

D + C

D – C

PIPELINE

ADC

VIN + D

VIN – D

SERIAL

LVDS

D + D

D – D

PIPELINE

ADC

VREF

FCO+

FCO–

SENSE

0.5V

–

DATA RATE

REFT

REFB

REF

SELECT

MULTIPLIER

1.8 V supply operation

Serial port control

SERIAL PORT

INTERFACE

DCO+

DCO–

Full-chip and individual-channel power-down modes

Flexible bit orientation

Built-in and custom digital test pattern generation

Programmable clock and data alignment

Programmable output resolution

Standby mode

SCLK/DTP

RBIASAGND CSB SDIO/ODM

CLK+ CLK–

Figure 1.

capturing data on the output and a frame clock (FCO) for

signaling a new output byte are provided. Individual channel

power-down is supported and typically consumes 2 mW when

all channels are disabled.

APPLICATIONS

Medical imaging and nondestructive ultrasound

Portable ultrasound and digital beam forming systems

Quadrature radio receivers

Diversity radio receivers

Tape drives

Optical networking

The ADC contains several features designed to maximize

flexibility and minimize system cost, such as programmable

clock and data alignment and programmable digital test pattern

generation. The available digital test patterns include built-in

deterministic and pseudorandom patterns, along with custom user-

defined test patterns entered via the serial port interface (SPI®).

Test equipment

The AD9259 is available in a Pb-free, 48-lead LFCSP package. It is

specified over the industrial temperature range of −40°C to +85°C.

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

The AD9259 is a quad, 14-bit, 50 MSPS analog-to-digital

converter (ADC) with an on-chip sample-and-hold circuit that

is designed for low cost, low power, small size, and ease of use.

The product operates at a conversion rate of up to 50 MSPS and

is optimized for outstanding dynamic performance and low

power in applications where a small package size is critical.

1. Small Footprint. Four ADCs are contained in a small, space-

saving package; low power of 98 mW/channel at 50 MSPS.

2. Ease of Use. A data clock output (DCO) operates up to

350 MHz and supports double data rate operation (DDR).

3. User Flexibility. Serial port interface (SPI) control offers a wide

range of flexible features to meet specific system requirements.

The ADC requires a single 1.8 V power supply and LVPECL-/

CMOS-/LVDS-compatible sample rate clock for full performance

operation. No external reference or driver components are

required for many applications.

4. Pin-Compatible Family. This includes the AD9287 (8-bit),

AD9219 (10-bit), and AD9228 (12-bit).

The ADC automatically multiplies the sample rate clock for the

appropriate LVDS serial data rate. A data clock (DCO) for

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

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AD9259BCPZRL7-50 替代型号

型号	品牌	替代类型	描述	数据表
AD9259ABCPZ-50	ADI	完全替代	Quad, 14-Bit, 50 MSPS Serial LVDS 1.8 V ADC
AD9259ABCPZRL7-50	ADI	完全替代	Quad, 14-Bit, 50 MSPS Serial LVDS 1.8 V ADC
AD9259BCPZ-50	ADI	类似代替	Quad, 14-bit, 50 MSPS Serial LVDS 1.8 V A/D Converter

与AD9259BCPZRL7-50相关器件

型号	品牌	获取价格	描述	数据表
AD9260	ADI	获取价格	High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate
AD9260AS	ADI	获取价格	High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate
AD9260ASRL	ROCHESTER	获取价格	1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44, MS-022AB, MQFP-44
AD9260ASZ	ROCHESTER	获取价格	1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44, LEAD FREE, MS-022AB, MQFP-44
AD9260ASZRL	ADI	获取价格	16-Bit High Speed Oversampled A/D Converter
AD9260EB	ADI	获取价格	High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate
AD9260-EB	ADI	获取价格	High Speed ADC USB FIFO Evaluation Kit
AD9261	ADI	获取价格	16-Bit, 10 MHz Bandwidth, 30 MSPS to 160 MSPS Continuous Time Sigma-Delta ADC
AD9261BCPZ-10	ADI	获取价格	16-Bit, 10 MHz Bandwidth, 30 MSPS to 160 MSPS Continuous Time Sigma-Delta ADC
AD9261BCPZ-10	ROCHESTER	获取价格	DELTA-SIGMA ADC, QCC48, 7 X 7 MM, ROHS COMPLIANT, MO-220VKKD-2, LFCSP-48

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