16-Bit, 125 MSPS/105 MSPS/80 MSPS,
1.8 V Analog-to-Digital Converter
AD9265
FEATURES
PRODUCT HIGHLIGHTS
SNR = 79.0 dBFS @ 70 MHz and 125 MSPS
SFDR = 93 dBc @ 70 MHz and 125 MSPS
Low power: 373 mW @ 125 MSPS
1.8 V analog supply operation
1.8 V CMOS or LVDS output supply
Integer 1-to-8 input clock divider
IF sampling frequencies to 300 MHz
−154.3 dBm/Hz small signal input noise with 200 Ω input
impedance @ 70 MHz and 125 MSPS
Optional on-chip dither
Programmable internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
1. On-chip dither option for improved SFDR performance
with low power analog input.
2. Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 300 MHz.
3. Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating 1.8 V CMOS or
LVDS outputs.
4. Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock duty cycle stabilizer, DCS, power-down, test
modes, and voltage reference mode.
5. Pin compatibility with the AD9255, allowing a simple
migration from 16 bits down to 14 bits.
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
APPLICATIONS
Communications
Multimode digital receivers (3G)
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX,
and TD-SCDMA
Smart antenna systems
General-purpose software radios
Broadband data applications
Ultrasound equipment
FUNCTIONAL BLOCK DIAGRAM
SENSE RBIAS PDWN
AGND AVDD (1.8V)
LVDS LVDS_RS
REFERENCE
VREF
AD9265
VCM
DRVDD (1.8V)
VIN+
TRACK-AND-HOLD
VIN–
OUTPUT
ADC
16-BIT
CORE
STAGING
CMOS OR
LVDS
16
16
DITHER
D15 TO D0
OR
(DDR)
CLK+
CLOCK
MANAGEMENT
CLK–
SYNC
SERIAL PORT
DCO
SVDD SCLK/ SDIO/ CSB
DFS DCS
Figure 1.
Rev. A
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