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AD9262_17

更新时间: 2024-10-29 00:58:27
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亚德诺 - ADI /
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33页 1209K
描述
30 MSPS to 160 MSPS Dual Continuous Time Sigma-Delta ADC

AD9262_17 数据手册

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16-Bit, 2.5 MHz/5 MHz/10 MHz, 30 MSPS to  
160 MSPS Dual Continuous Time Sigma-Delta ADC  
AD9262  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
AVDD  
DRVDD  
SNR: 83 dB (85 dBFS) to 10 MHz input  
SFDR: −87 dBc to 10 MHz input  
Noise figure: 15 dB  
Input impedance: 1 kΩ  
Power: 600 mW  
1.8 V analog supply operation  
1.8 V to 3.3 V output supply  
Selectable bandwidth  
2.5 MHz/5 MHz/10 MHz real  
5 MHz/10 MHz/20 MHz complex  
Output data rate: 30 MSPS to 160 MSPS  
Integrated dc and quadrature correction  
Integrated decimation filters  
Integrated sample rate converter  
On-chip PLL clock multiplier  
On-chip voltage reference  
ORA  
VIN+A  
VIN–A  
D15A  
SAMPLE  
RATE  
LOW-PASS  
DECIMATION  
FILTER  
CT Σ-Δ  
DC  
CORRECT  
CMOS  
MODULATOR  
BUFFER  
CONVERTER  
D0A  
GAIN  
ADJ  
QUADRATURE  
ERROR  
ESTIMATE  
VREF  
CFILT  
PHASE  
ADJ  
AD9262  
DCO  
D15B  
D0B  
VIN–B  
VIN+B  
LOW-PASS  
DECIMATION  
FILTER  
SAMPLE  
RATE  
CONVERTER  
CT Σ-Δ  
MODULATOR  
DC  
CORRECT  
CMOS  
BUFFER  
CLK+  
CLK–  
PHASE-  
LOCKED  
LOOP  
SERIAL  
INTERFACE  
ORB  
AGND  
SDIO SCLK CSB DGND  
Figure 1  
The AD9262 incorporates an integrated dc correction and  
quadrature estimation block that corrects for gain and phase  
mismatch between the two channels. This functional block  
proves invaluable in complex signal processing applications  
such as direct conversion receivers.  
Offset binary, Gray code, or twos complement data format  
Serial control interface (SPI)  
APPLICATIONS  
The digital output data is presented in offset binary, Gray code,  
or twos complement format. A data clock output (DCO) is  
provided to ensure proper timing with the receiving logic. The  
AD9262 has the added feature of interleaving Channel A and  
Channel B data onto one 16-bit bus, simplifying on-board routing.  
Baseband quadrature receivers: CDMA2000, W-CDMA,  
multicarrier GSM/EDGE, 802.16x, and LTE  
Quadrature sampling instrumentation  
Medical equipment  
Radio detection and ranging (RADAR)  
The ADC is available in three different bandwidth options of  
2.5 MHz, 5 MHz, and 10 MHz, and operates on a 1.8 V analog  
supply and a 1.8 V to 3.3 V digital supply, consuming 600 mW.  
The AD9262 is available in a 64-lead LFCSP and is specified  
over the industrial temperature range (−40°C to +85°C).  
GENERAL DESCRIPTION  
The AD9262 is a dual channel, 16-bit analog-to-digital conver-  
ter (ADC) based on a continuous time (CT) sigma-delta (Σ-Δ)  
architecture that achieves −87 dBc of dynamic range over a  
10 MHz input bandwidth. The integrated features and characteris-  
tics unique to the continuous time Σ-Δ architecture significantly  
simplify its use and minimize the need for external components.  
PRODUCT HIGHLIGHTS  
1. Continuous time Σ-Δ architecture efficiently achieves high  
dynamic range and wide bandwidth.  
The AD9262 has a resistive input impedance that relaxes the  
requirements of the driver amplifier. In addition, a 32× oversam-  
pled fifth-order continuous time loop filter significantly attenuates  
out-of-band signals and aliases, reducing the need for external  
filters at the input.  
2. Passive input structure reduces or eliminates the require-  
ments for a driver amplifier.  
3. An oversampling ratio of 32× and high order loop filter  
provide excellent alias rejection reducing or eliminating the  
need for antialiasing filters.  
4. An integrated decimation filter, sample rate converter, PLL  
clock multiplier, and voltage reference provide ease of use.  
5. Integrated dc correction and quadrature error correction.  
6. Operates from a single 1.8 V analog power supply and  
1.8 V to 3.3 V output supply.  
An external clock input or the integrated integer-N PLL provides  
the 640 MHz internal clock needed for the oversampled conti-  
nuous time Σ-Δ modulator. On-chip decimation filters and sample  
rate converters reduce the modulator data rate from 640 MSPS to a  
user-defined output data rate between 30 MSPS and 160 MSPS,  
enabling a more efficient and direct interface.  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2010 Analog Devices, Inc. All rights reserved.  
 
 
 
 
 

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