Datasheet > AD73360LARZ

AD73360LARZ

更新时间： 2024-02-12 18:16:49

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
35页	281K
描述
Six-Input Channel Analog Front End

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中文翻译

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技术参数
数据手册
替代型号

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AD73360LARZ 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOP,	针数：	28
Reach Compliance Code：	unknown	风险等级：	5.6
JESD-30 代码：	R-PDSO-G28	JESD-609代码：	e3
长度：	17.9 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	28
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	认证状态：	COMMERCIAL
座面最大高度：	2.65 mm	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	TELECOM CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
宽度：	7.5 mm	Base Number Matches：	1

AD73360LARZ 数据手册

AD73360

APPENDIX B

In Step 1, the device has just been reset and the on first output

event the AD73360 presents an invalid ADC sample word¹.

Once this word has been received the DSP can begin transmit-

ting programming information to the AD73360. The first con-

trol word sets the sampling rate at 8 kHz. In Step 2, the DSP

instructs the AD73360 to power up channels 1 and 2 and sets

the gain of each. No data is read from the AD73360 at this

point. Steps 3 and 4 set the reference and places the part into

Mixed Mode. In Steps 5 and 6 valid ADC results are read from

the AD73360 and in Step 7 the DSP sends an instruction to the

AD73360 to change the gain of Channel 1.

Programming a Single AD73360 for Mixed Mode Operation

This section describes a typical sequence in programming a

single AD73360 to operate in Mixed Mode. The device is con-

figured in Nonframe Sync Loop-Back (see Figure 14), which

allows the DSP’s Tx Register to determine how many words are

sent to the device during one sample interval. In Nonframe

Sync Loop-Back mode care must be taken when writing to the

AD73360 that an ADC result or register read result contained

in the device’s serial register is not corrupted by a write. The

best way to avoid this is to only write control words when the

AD73360 has no more data to send. This can limit the number

of times a DSP can write to the AD73360 and is dependant on

the SCLK speed and the number of channels powered up. In

this example it is assumed that there are only two channels

powered up and that there is adequate time to transmit data

after the ADC results have been read.

NOTE

¹This sequence assumes that the DSP SPORT’s Rx and Tx interrupts are

enabled. It is important to ensure there is no latency (separation) between

control words in a cascade configuration. This is especially the case when

programming Control Register B, as it contains settings for SCLK and

DMCLK rates.

SET 8kHz SAMPLING

DSP Tx REG

DEVICE 1

ADC WORD 1*

0000 0000 0000 0000

DSP Rx REG

CONTROL WORD

1000 0001 0000 0011

DON'T CARE

0000 0000 0000 0000

STEP 1

POWER UP CHANNEL 1&2 AND SET GAINS

DSP Rx REG

DSP Tx REG

DEVICE 1

CONTROL WORD

ADC WORD 1*

DON'T CARE

0000 0000 0000 0000

1000 0011 1111 1010

1011 1001 0000 0011

STEP 2

POWER UP REFERENCE

DSP Rx REG

DSP Tx REG

DEVICE 1

CONTROL WORD

ADC WORD 1*

DON'T CARE

0000 0000 0000 0000

1000 0010 1110 0000

1011 1011 1111 1010

STEP 3

SET MIXED MODE

DSP Rx REG

DSP Tx REG

DEVICE 1

CONTROL WORD

ADC WORD 1*

DON'T CARE

0000 0000 0000 0000

1000 0000 0000 0010

1011 1010 1110 0000

STEP 4

RECEIVE VALID ADC DATA

DSP Rx REG

DSP Tx REG

DEVICE 1

CONTROL WORD

ADC WORD 1

1000 0000 0000 0000

0111 1111 1111 1111

1000 0000 0000 0000

STEP 5

RECEIVE VALID ADC DATA

DSP Rx REG

DSP Tx REG

DEVICE 1

CONTROL WORD

ADC WORD 2

1111 0000 0000 0000

0111 1111 1111 1111

1111 0000 0000 0000

STEP 6

CHANGE GAIN ON CHANNEL 1

DSP Rx REG

DSP Tx REG

DEVICE 1

CONTROL WORD

INVALID DATA

ADC WORD 2

1111 0000 0000 0000

1000 0011 1000 0010

xxxx xxxx xxxx xxxx

STEP 7

*ADC DATA RECEIVED BY THE DSP DURING THE PROGRAMMING PHASE SHOULD NOT BE CONSIDERED VALID RESULTS

Figure 33. Programming a Single AD73360 for Operation in Mixed Mode

REV. A

–29–

1...26 27 282930 31 32...35

中文翻译

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AD73360LARZ 替代型号

型号	品牌	替代类型	描述	数据表
AD73360LAR	ADI	功能相似	Six-Input Channel Analog Front End

与AD73360LARZ相关器件

型号	品牌	获取价格	描述	数据表
AD73360LARZ-REEL	ROCHESTER	获取价格	SPECIALTY TELECOM CIRCUIT, PDSO28, SOIC-28
AD73360LARZ-REEL	ADI	获取价格	Six-Input Channel Analog Front End
AD73360LARZ-REEL7	ADI	获取价格	IC SPECIALTY TELECOM CIRCUIT, PDSO28, SOIC-28, Telecom IC:Other
AD7339	ADI	获取价格	5 V Integrated High Speed ADC/Quad DAC System
AD7339BS	ADI	获取价格	5 V Integrated High Speed ADC/Quad DAC System
AD7339BSZ-REEL	ADI	获取价格	8-Bit I/O Port
AD734	ADI	获取价格	10 MHz, 4-Quadrant Multiplier/Divider
AD73411	ADI	获取价格	Low-Power Analog Front End with DSP Microcomputer
AD73411BB-40	ADI	获取价格	Low-Power Analog Front End with DSP Microcomputer
AD73411BB-80	ADI	获取价格	Low-Power Analog Front End with DSP Microcomputer

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