Datasheet > AD73360LARZ

AD73360LARZ

更新时间： 2024-02-06 11:18:20

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
35页	281K
描述
Six-Input Channel Analog Front End

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技术参数
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AD73360LARZ 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOP,	针数：	28
Reach Compliance Code：	unknown	风险等级：	5.6
JESD-30 代码：	R-PDSO-G28	JESD-609代码：	e3
长度：	17.9 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	28
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	认证状态：	COMMERCIAL
座面最大高度：	2.65 mm	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	TELECOM CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
宽度：	7.5 mm	Base Number Matches：	1

AD73360LARZ 数据手册

AD73360

APPENDIX D

In Step 4, another sample interval has occurred and the

SDOFS on both devices are raised. Device 2 sends an ADC

result to the DSP and Device 1 sends an ADC result to Device

2. The remaining time before the next sample interval can be

used to program more registers in the AD73360s. Care must be

taken that the subsequent writes do not overlap the next sample

interval to avoid corrupting the data. The control words are

written as Device 2, Device 1, Device 2, etc.

Configuring a Cascade of Two AD73360s to Operate in Mixed

Mode

This section describes a typical sequence of control words that

would be sent to a cascade of two AD73360s to configure them

for operation in Mixed Mode. It is not intended to be a defini-

tive initialization sequence, but will show users the typical input/

output events that occur in the programming and operation

phases¹. This description panel refers to Figure 35.

Step 5 shows the DSP starting to program the ADC Control

case the first write operation programs Control Register D to

power up ADC channels 1 and 2 with gains of 0 dBs. This step

can be repeated until all the registers have been programmed.

The devices should be programmed in the order Device 2,

Device 1, Device 2, etc.

In Step 1, we have the first output sample event following device

reset. The SDOFS signal is raised on both devices simulta-

neously, which prepares the DSP Rx register to accept the ADC

word from Device 2 while SDOFS from Device 1 becomes an

SDIFS to Device 2. The cascade is configured as nonFSLB,

which means that the DSP has control over what is transmitted

to the cascade. The DSP will receive an invalid ADC word from

Device 2 and simultaneously Device 2 is receiving an invalid

ADC word from Device 1. As both AD73360s are in Program

Mode there is only one output event per sample period. The

DSP can now send a control word to the AD73360s.

In Step 6, the DSP transmits a control word for Device 2. This

control word set the Device count to 2 and instructs the AD73360

to go into Mixed Mode. When Device 1 receives this control

word it will decrement the address field and generate an SDOFS

to pass it on to Device 2.

In Step 2, the DSP has finished transmitting the control word to

Device 1. Device 1 recognizes that this word is not intended for

it so it will decrement the address field and generate and SDOFS

and proceed to transmit the control word to the next device in

the chain. At this point the DSP should transmit a control word

for Device 1. This will ensure that both devices receive, and act

upon, the control words at the same time.

In Step 7, the DSP transmits a control word for Device 1. This

should happen as Device 1 is transmitting the control word for

Device 2 to ensure that both device change into Mixed Mode at

the same time.

In Step 8, we begin receiving the first valid ADC words from

the cascade.

Step 3 shows completion of the first series of control word writes.

The DSP has now received an ADC word from Device 2 and

each device has received a control word that addresses Control

gramming a cascade of AD73360s in NonFSLB it is important

to ensure that control words which affect the operation of the

serial port are received by all devices simultaneously.

It is assumed that there is sufficient time to transmit all the

required Control Words in the allotted time.

NOTE

¹This sequence assumes that the DSP SPORT’s Rx and Tx interrupts are

enabled. It is important to ensure there is no latency (separation) between

control words in a cascade configuration. This is especially the case when

programming Control Register B, as it contains settings for SCLK and

DMCLK rates.

–32–

REV. A

1...29 30 313233 34 35

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AD73360LARZ 替代型号

型号	品牌	替代类型	描述	数据表
AD73360LAR	ADI	功能相似	Six-Input Channel Analog Front End

与AD73360LARZ相关器件

型号	品牌	获取价格	描述	数据表
AD73360LARZ-REEL	ROCHESTER	获取价格	SPECIALTY TELECOM CIRCUIT, PDSO28, SOIC-28
AD73360LARZ-REEL	ADI	获取价格	Six-Input Channel Analog Front End
AD73360LARZ-REEL7	ADI	获取价格	IC SPECIALTY TELECOM CIRCUIT, PDSO28, SOIC-28, Telecom IC:Other
AD7339	ADI	获取价格	5 V Integrated High Speed ADC/Quad DAC System
AD7339BS	ADI	获取价格	5 V Integrated High Speed ADC/Quad DAC System
AD7339BSZ-REEL	ADI	获取价格	8-Bit I/O Port
AD734	ADI	获取价格	10 MHz, 4-Quadrant Multiplier/Divider
AD73411	ADI	获取价格	Low-Power Analog Front End with DSP Microcomputer
AD73411BB-40	ADI	获取价格	Low-Power Analog Front End with DSP Microcomputer
AD73411BB-80	ADI	获取价格	Low-Power Analog Front End with DSP Microcomputer

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