Datasheet > AD6643

AD6643

更新时间： 2022-10-08 17:27:42

品牌	Logo	应用领域
亚德诺 - ADI		接收机
页数	文件大小	规格书
36页	1331K
描述
Dual IF Receiver 1.8 V supply voltages Internal ADC voltage reference

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中文翻译

获取价格

数据手册

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AD6643 数据手册

AD6643

Default

Value

(Hex)

Addr Register

(Hex) Name

Bit 7

(MSB)

Bit 0

(LSB)

Default Notes/

Comments

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0x1D User Test

User Test Pattern 3[7:0]

User Test Pattern 3[1ꢀ:8]

User Test Pattern 4[7:0]

User Test Pattern 4[1ꢀ:8]

BIST signature[7:0]

0x00

Pattern 3 LSB

(global)

0x1E

0x1F

0x20

0x24

0x2ꢀ

User Test

Pattern 3

MSB (global)

User Test

Pattern 4 LSB

(global)

User Test

Pattern 4

MSB (global)

0x00

BIST

signature

LSB (local)

Read only

BIST

signature

MSB (local)

BIST signature[1ꢀ:8]

0x00

Digital Feature Control Registers

0x3A

Sync control

(global)

Open

Open Open

Open

Open Clock

Master

sync

enable

0 = off

1 = on

Control register

to synchronize

the clock divider

divider

sync enable

0 = off

1 = on

0x3C

NSR control

(local)

Open

NSR mode

NSR

0x00

0x1C

Noise shaping

requantizer (NSR)

controls

000 = 22% BW mode

001 = 33% BW mode

enable

0 = off

1 = on

0x3E

0xꢀ9

NSR tuning

word (local)

Open

NSR tuning word

See the Noise Shaping Requantizer (NSR) section

Equations for the tuning word are dependent on the NSR mode

NSR

frequency

tuning word

SYNC pin

control

(local)

Open Open

Open

Open SYNC pin

sensitivity

0 = sync on

high level

SYNC pin

edge

sensitivity

0 = sync

negative

edge

1 = sync on

edge

1 = sync

positive

edge

¹The channel index register at Address 0x0ꢀ should be set to 0x03 (default) when writing to Address 0x00.

Bit 1—Clock Divider Sync Enable

MEMORY MAP REGISTER DESCRIPTION

Bit 1 gates the sync pulse to the clock divider. The sync signal is

enabled when Bit 1 is high and Bit 0 is high. This is continuous

sync mode.

For more information on functions controlled in Register 0x00

to Register 0x25, see the AN-877 Application Note, Interfacing

to High Speed ADCs via SPI, available at www.analog.com.

Bit 0—Master Sync Buffer Enable

Sync Control (Register 0x3A)

Bits[7:3]—Reserved

Bit 0 must be set high to enable any of the sync functions. If the

sync capability is not used this bit should remain low to

conserve power.

Bit 2—Clock Divider Next Sync Only

If the master sync enable buffer bit (Address 0x3A, Bit0) and

the clock divider sync enable bit (Address 0x3A, Bit 1) are high,

Bit 2 allows the clock divider to sync to the first sync pulse it

receives and to ignore the rest. The clock divider sync enable bit

(Address 0x3A, Bit 1) resets after it syncs.

Rev. 0 | Page 32 of 36

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中文翻译

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与AD6643相关器件

型号	品牌	获取价格	描述	数据表
AD6643_12	ADI	获取价格	Dual IF Receiver
AD6643_17	ADI	获取价格	Dual IF Receiver
AD6643-200EBZ	ADI	获取价格	Dual IF Receiver 1.8 V supply voltages Internal ADC voltage reference
AD6643-250EBZ	ADI	获取价格	Dual IF Receiver
AD6643BCPZ-200	ADI	获取价格	Dual IF Receiver 1.8 V supply voltages Internal ADC voltage reference
AD6643BCPZ-250	ADI	获取价格	Dual IF Receiver
AD6643BCPZRL7-200	ADI	获取价格	Dual IF Receiver 1.8 V supply voltages Internal ADC voltage reference
AD6643BCPZRL7-250	ADI	获取价格	Dual IF Receiver
AD6644	ADI	获取价格	14-Bit, 40 MSPS/65 MSPS A/D Converter
AD6644_17	ADI	获取价格	Analog-to-Digital Converter

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