Dual IF Receiver
AD6643
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD
11-bit, 250 MSPS output data rate per channel
Performance with NSR enabled
SNR: 74.5 dBFS in a 55 MHz band to 90 MHz at 250 MSPS
SNR: 72.0 dBFS in a 82 MHz band to 90 MHz at 250 MSPS
Performance with NSR disabled
SNR: 66.2 dBFS up to 90 MHz at 250 MSPS
SFDR: 85 dBc up to 185 MHz at 250 MSPS
Total power consumption: 706 mW at 200 MSPS
1.8 V supply voltages
AD6643
DCO±
D0±
14
14
11
VIN+A
VIN–A
VCM
NOISE SHAPING
REQUANTIZER
PIPELINE
ADC
11
VIN+B
VIN–B
NOISE SHAPING
REQUANTIZER
PIPELINE
ADC
D10±
OEB
REFERENCE
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Internal ADC voltage reference
CLOCK
DIVIDER
SYNC
PDWN
SERIAL PORT
Flexible analog input range
SCLK SDIO
CSB
CLK+ CLK–
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
Differential analog inputs with 400 MHz bandwidth
95 dB channel isolation/crosstalk
NOTES
1. THE D0± TO D10± PINS REPRESENT BOTH THE CHANNEL A
AND CHANNEL B LVDS OUTPUT DATA.
Figure 1.
Serial port control
Energy saving power-down modes
APPLICATIONS
Communications
Diversity radio and smart antenna (MIMO) systems
Multimode digital receivers (3G)
WCDMA, LTE, CDMA2000
WiMAX, TD-SCDMA
I/Q demodulation systems
General-purpose software radios
GENERAL DESCRIPTION
The AD6643 is an 11-bit, 200 MSPS/250 MSPS, dual-channel
intermediate frequency (IF) receiver specifically designed to
support multi-antenna systems in telecommunication
applications where high dynamic range performance, low power,
and small size are desired.
Each ADC output is connected internally to an NSR block. The
integrated NSR circuitry allows for improved SNR performance in
a smaller frequency band within the Nyquist bandwidth. The
device supports two different output modes selectable via the SPI.
With the NSR feature enabled, the outputs of the ADCs are
processed such that the AD6643 supports enhanced SNR per-
formance within a limited portion of the Nyquist bandwidth
while maintaining an 11-bit output resolution.
The device consists of two high performance analog-to-digital
converters (ADCs) and noise shaping requantizer (NSR) digital
blocks. Each ADC consists of a multistage, differential pipelined
architecture with integrated output error correction logic, and
each ADC features a wide bandwidth switched capacitor sampling
network within the first stage of the differential pipeline. An
integrated voltage reference eases design considerations. A duty
cycle stabilizer (DCS) compensates for variations in the ADC
clock duty cycle, allowing the converters to maintain excellent
performance.
The NSR block can be programmed to provide a bandwidth
of either 22% or 33% of the sample clock. For example, with a
sample clock rate of 185 MSPS, the AD6643 can achieve up to
75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode and
up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode.
(continued on Page 3)
Rev. C
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Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2012 Analog Devices, Inc. All rights reserved.
Technical Support
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