Datasheet > AD6643BCPZRL7-250

AD6643BCPZRL7-250

更新时间： 2024-01-21 16:30:51

品牌	Logo	应用领域
亚德诺 - ADI		电信电信集成电路
页数	文件大小	规格书
41页	1285K
描述
Dual IF Receiver

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

AD6643BCPZRL7-250 技术参数

Source Url Status Check Date：	2013-05-01 14:56:15.913	是否无铅：	含铅
是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	QFN	包装说明：	HVQCCN, LCC64,.35SQ,20
针数：	64	Reach Compliance Code：	compliant
ECCN代码：	5A991.B	HTS代码：	8542.39.00.01
风险等级：	5.56	JESD-30 代码：	S-XQCC-N64
JESD-609代码：	e3	长度：	9 mm
湿度敏感等级：	3	功能数量：	2
端子数量：	64	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装等效代码：	LCC64,.35SQ,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	电源：	1.8 V
认证状态：	Not Qualified	座面最大高度：	1 mm
子类别：	Other Telecom ICs	最大压摆率：	0.275 mA
标称供电电压：	1.8 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	RF AND BASEBAND CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	9 mm	Base Number Matches：	1

AD6643BCPZRL7-250 数据手册

浏览型号AD6643BCPZRL7-250的Datasheet PDF文件第2页

浏览型号AD6643BCPZRL7-250的Datasheet PDF文件第3页

浏览型号AD6643BCPZRL7-250的Datasheet PDF文件第4页

浏览型号AD6643BCPZRL7-250的Datasheet PDF文件第5页

浏览型号AD6643BCPZRL7-250的Datasheet PDF文件第6页

浏览型号AD6643BCPZRL7-250的Datasheet PDF文件第7页

Dual IF Receiver

AD6643

Data Sheet

FEATURES

FUNCTIONAL BLOCK DIAGRAM

AVDD

AGND

DRVDD

11-bit, 250 MSPS output data rate per channel

Performance with NSR enabled

SNR: 74.5 dBFS in a 55 MHz band to 90 MHz at 250 MSPS

SNR: 72.0 dBFS in a 82 MHz band to 90 MHz at 250 MSPS

Performance with NSR disabled

SNR: 66.2 dBFS up to 90 MHz at 250 MSPS

SFDR: 85 dBc up to 185 MHz at 250 MSPS

Total power consumption: 706 mW at 200 MSPS

1.8 V supply voltages

AD6643

DCO±

D0±

VIN+A

VIN–A

VCM

NOISE SHAPING

REQUANTIZER

PIPELINE

ADC

VIN+B

VIN–B

NOISE SHAPING

REQUANTIZER

PIPELINE

ADC

D10±

OEB

REFERENCE

LVDS (ANSI-644 levels) outputs

Integer 1-to-8 input clock divider (625 MHz maximum input)

Internal ADC voltage reference

CLOCK

DIVIDER

SYNC

PDWN

SERIAL PORT

Flexible analog input range

SCLK SDIO

CSB

CLK+ CLK–

1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)

Differential analog inputs with 400 MHz bandwidth

95 dB channel isolation/crosstalk

NOTES

1. THE D0± TO D10± PINS REPRESENT BOTH THE CHANNEL A

AND CHANNEL B LVDS OUTPUT DATA.

Figure 1.

Serial port control

Energy saving power-down modes

APPLICATIONS

Communications

Diversity radio and smart antenna (MIMO) systems

Multimode digital receivers (3G)

WCDMA, LTE, CDMA2000

WiMAX, TD-SCDMA

I/Q demodulation systems

General-purpose software radios

GENERAL DESCRIPTION

The AD6643 is an 11-bit, 200 MSPS/250 MSPS, dual-channel

intermediate frequency (IF) receiver specifically designed to

support multi-antenna systems in telecommunication

applications where high dynamic range performance, low power,

and small size are desired.

Each ADC output is connected internally to an NSR block. The

integrated NSR circuitry allows for improved SNR performance in

a smaller frequency band within the Nyquist bandwidth. The

device supports two different output modes selectable via the SPI.

With the NSR feature enabled, the outputs of the ADCs are

processed such that the AD6643 supports enhanced SNR per-

formance within a limited portion of the Nyquist bandwidth

while maintaining an 11-bit output resolution.

The device consists of two high performance analog-to-digital

converters (ADCs) and noise shaping requantizer (NSR) digital

blocks. Each ADC consists of a multistage, differential pipelined

architecture with integrated output error correction logic, and

each ADC features a wide bandwidth switched capacitor sampling

network within the first stage of the differential pipeline. An

integrated voltage reference eases design considerations. A duty

cycle stabilizer (DCS) compensates for variations in the ADC

clock duty cycle, allowing the converters to maintain excellent

performance.

The NSR block can be programmed to provide a bandwidth

of either 22% or 33% of the sample clock. For example, with a

sample clock rate of 185 MSPS, the AD6643 can achieve up to

75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode and

up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode.

(continued on Page 3)

Rev. C

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

12 3 4 5 6 7...41

下载PDF

与AD6643BCPZRL7-250相关器件

型号	品牌	描述	获取价格	数据表
AD6644	ADI	14-Bit, 40 MSPS/65 MSPS A/D Converter	获取价格
AD6644_17	ADI	Analog-to-Digital Converter	获取价格
AD6644AST-40	ADI	14-Bit, 40 MSPS/65 MSPS A/D Converter	获取价格
AD6644AST-65	ADI	14-Bit, 40 MSPS/65 MSPS A/D Converter	获取价格
AD6644ASTZ-40	ADI	Analog-to-Digital Converter	获取价格
AD6644ASTZ-65	ROCHESTER	1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP52, LOW PROFILE, PLASTIC, MS-026B	获取价格

产品中心

服务支持

精选活动

关于我们

帮助中心

AD6643BCPZRL7-250

AD6643BCPZRL7-250 技术参数

AD6643BCPZRL7-250 数据手册

与AD6643BCPZRL7-250相关器件

与AD6643BCPZRL7-250相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AD6643BCPZRL7-250

AD6643BCPZRL7-250 技术参数

AD6643BCPZRL7-250 数据手册

与AD6643BCPZRL7-250相关器件

与AD6643BCPZRL7-250相关文章

您还可以找

您在本页遇到什么问题？