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AD6643BCPZ-200 PDF预览

AD6643BCPZ-200

更新时间: 2024-02-14 17:01:26
品牌 Logo 应用领域
亚德诺 - ADI 接收机
页数 文件大小 规格书
36页 1331K
描述
Dual IF Receiver 1.8 V supply voltages Internal ADC voltage reference

AD6643BCPZ-200 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN, LCC64,.35SQ,20针数:64
Reach Compliance Code:compliantECCN代码:5A991.B
HTS代码:8542.39.00.01风险等级:2.14
JESD-30 代码:S-XQCC-N64JESD-609代码:e3
长度:9 mm湿度敏感等级:3
功能数量:2端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC64,.35SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:1.8 V认证状态:Not Qualified
座面最大高度:1 mm子类别:Other Telecom ICs
最大压摆率:0.26 mA标称供电电压:1.8 V
表面贴装:YES电信集成电路类型:RF AND BASEBAND CIRCUIT
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:9 mmBase Number Matches:1

AD6643BCPZ-200 数据手册

 浏览型号AD6643BCPZ-200的Datasheet PDF文件第2页浏览型号AD6643BCPZ-200的Datasheet PDF文件第3页浏览型号AD6643BCPZ-200的Datasheet PDF文件第4页浏览型号AD6643BCPZ-200的Datasheet PDF文件第5页浏览型号AD6643BCPZ-200的Datasheet PDF文件第6页浏览型号AD6643BCPZ-200的Datasheet PDF文件第7页 
Dual IF Receiver  
AD6643  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
AVDD  
AGND  
DRVDD  
Performance with NSR enabled  
SNR: 76.1 dBFS in a 40 MHz band to 90 MHz at 185 MSPS  
SNR: 73.6 dBFS in a 60 MHz band to 90 MHz at 185 MSPS  
Performance with NSR disabled  
SNR: 66.5 dBFS up to 90 MHz at 185 MSPS  
SFDR: 88 dBc up to 185 MHz at 185 MSPS  
Total power consumption: 706 mW at 200 MSPS  
1.8 V supply voltages  
LVDS (ANSI-644 levels) outputs  
Integer 1-to-8 input clock divider (625 MHz maximum input)  
Internal ADC voltage reference  
AD6643  
DCO±  
D0±  
14  
14  
11  
VIN+A  
VIN–A  
VCM  
NOISE SHAPING  
REQUANTIZER  
PIPELINE  
ADC  
11  
VIN+B  
VIN–B  
NOISE SHAPING  
REQUANTIZER  
PIPELINE  
ADC  
D10±  
OEB  
REFERENCE  
CLOCK  
DIVIDER  
SYNC  
PDWN  
SERIAL PORT  
Flexible analog input range  
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)  
Differential analog inputs with 400 MHz bandwidth  
95 dB channel isolation/crosstalk  
Serial port control  
Energy saving power-down modes  
SCLK SDIO  
CSB  
CLK+ CLK–  
NOTES  
1. THE D0± TO D10± PINS REPRESENT BOTH THE CHANNEL A  
AND CHANNEL B LVDS OUTPUT DATA.  
Figure 1.  
User-configurable, built-in self test (BIST) capability  
APPLICATIONS  
Communications  
Diversity radio and smart antenna (MIMO) systems  
Multimode digital receivers (3G)  
WCDMA, LTE, CDMA2000  
WiMAX, TD-SCDMA  
I/Q demodulation systems  
General-purpose software radios  
GENERAL DESCRIPTION  
The AD6643 is an 11-bit, 200 MSPS, dual-channel intermediate  
frequency (IF) receiver specifically designed to support multi-  
antenna systems in telecommunication applications where high  
dynamic range performance, low power, and small size are desired.  
Each ADC output is connected internally to an NSR block. The  
integrated NSR circuitry allows for improved SNR performance in  
a smaller frequency band within the Nyquist bandwidth. The  
device supports two different output modes selectable via the SPI.  
With the NSR feature enabled, the outputs of the ADCs are  
processed such that the AD6643 supports enhanced SNR per-  
formance within a limited portion of the Nyquist bandwidth  
while maintaining an 11-bit output resolution.  
The device consists of two high performance analog-to-digital  
converters (ADCs) and noise shaping requantizer (NSR) digital  
blocks. Each ADC consists of a multistage, differential pipelined  
architecture with integrated output error correction logic, and  
each ADC features a wide bandwidth switched capacitor sampling  
network within the first stage of the differential pipeline. An  
integrated voltage reference eases design considerations. A duty  
cycle stabilizer (DCS) compensates for variations in the ADC  
clock duty cycle, allowing the converters to maintain excellent  
performance.  
The NSR block can be programmed to provide a bandwidth  
of either 22% or 33% of the sample clock. For example, with a  
sample clock rate of 185 MSPS, the AD6643 can achieve up to  
75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode and  
up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode.  
(continued on Page 3)  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2011 Analog Devices, Inc. All rights reserved.  
 

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