Datasheet > AD5516_03

AD5516_03

更新时间： 2022-05-20 03:03:22

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
16页	228K
描述
16-Channel, 12-Bit Voltage-Output DAC with 14-Bit Increment Mode

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

AD5516_03 数据手册

AD5516

(V_DD= +4.75 V to +13.2 V, V_SS= –4.75 V to –13.2 V; AV_CC= 4.75 V to 5.25 V; DV_CC= 2.7 V to 5.25 V;

AGND = DGND = DACGND = 0 V; REF IN = 3 V. All outputs unloaded.

All specifications T_MINto T_MAX, unless otherwise noted.)

AC CHARACTERISTICS

Parameter^{1, 2}

A Version³

Unit

Conditions/Comments

Output Voltage Settling Time (Mode 1)⁴

AD5516–1

100 pF, 5 kW Load Full-Scale Change

␮s max

AD5516–2

AD5516–3

Output Voltage Settling Time (Mode 2)⁴

AD5516–1

100 pF, 5 kW Load, 127 Code Increment

2.5

3.35

0.85

␮s max

V/␮s typ

nV-s typ

AD5516–2

AD5516–3

Slew Rate

Digital-to-Analog Glitch Impulse

Digital Crosstalk

Analog Crosstalk

AD5516–1

AD5516–2

AD5516–3

Digital Feedthrough

Output Noise Spectral Density @ 10 kHz

AD5516–1

1 LSB Change around Major Carry

nV-s typ

150

350

700

nV/(Hz)^1/2typ

AD5516–2

AD5516–3

NOTES

¹See Terminology section.

²Guaranteed by design and characterization; not production tested.

³A version: Industrial temperature range –40∞C to +85∞C.

⁴Timed from the end of a write sequence and includes BUSY low time.

Specifications subject to change without notice.

(V_DD= +4.75 V to +13.2 V, V_SS= – 4.75 V to –13.2 V; AV_CC= 4.75 V to 5.25 V; DV_CC= 2.7 V to 5.25 V;

TIMING CHARACTERISTICS AGND = DGND = DACGND = 0 V. All specifications T_MINto T_MAX, unless otherwise noted.)

Limit at T_MIN, T_MAX

(A Version)

Parameter^{1, 2, 3}

Unit

Conditions/Comments

f_UPDATE1

f_UPDATE2

f_CLKIN

t₁

t₂

t₃

t₄

t₅

750

kHz max

MHz max

ns min

ns max

ns min

DAC Update Rate (Mode 1)

DAC Update Rate (Mode 2)

SCLK Frequency

SCLK High Pulsewidth

SCLK Low Pulsewidth

SYNC Falling Edge to SCLK Falling Edge Setup Time

D_INSetup Time

D_INHold Time

t₆

t₇

SCLK Falling Edge to SYNC Rising Edge

Minimum SYNC High Time (Standalone Mode)

Minimum SYNC High Time (Daisy-Chain Mode)

BUSY Rising Edge to SYNC Falling Edge

18th SCLK Falling Edge to SYNC Falling Edge (Standalone Mode)

SYNC Rising Edge to SCLK Rising Edge (Daisy-Chain Mode)

SCLK Rising Edge to D_OUTValid (Daisy-Chain Mode)

RESET Pulsewidth

400

200

t_7MODE2

t_8MODE1

t_9MODE2

t₁₀

t₁₁

t₁₂

NOTES

¹See Timing Diagrams in Figures 1 and 2.

²Guaranteed by design and characterization; not production tested.

³All input signals are specified with tr = tf = 5 ns (10% to 90% of DV_CC) and timed from a voltage level of (V_IL+ V_IH)/2.

⁴This is measured with the load circuit of Figure 3.

Specifications subject to change without notice.

REV. B

–3–

1 234 5 6 7...16

中文翻译

下载PDF

与AD5516_03相关器件

型号	品牌	获取价格	描述	数据表
AD5516-1	ADI	获取价格	16-Channel, 12-Bit Voltage-Output DAC with 14-Bit Increment Mode
AD5516-2	ADI	获取价格	16-Channel, 12-Bit Voltage-Output DAC with 14-Bit Increment Mode
AD5516-3	ADI	获取价格	16-Channel, 12-Bit Voltage-Output DAC with 14-Bit Increment Mode
AD5516ABC-1	ADI	获取价格	16-Channel, 12-Bit Voltage-Output DAC with 14-Bit Increment Mode
AD5516ABC-2	ADI	获取价格	16-Channel, 12-Bit Voltage-Output DAC with 14-Bit Increment Mode
AD5516ABC-2	ROCHESTER	获取价格	SERIAL INPUT LOADING, 14-BIT DAC, PBGA74, 12 X 12 MM, MO-192ABD-1, CSPBGA-74
AD5516ABC-3	ADI	获取价格	16-Channel, 12-Bit Voltage-Output DAC with 14-Bit Increment Mode
AD5516ABC-3	ROCHESTER	获取价格	SERIAL INPUT LOADING, 14-BIT DAC, PBGA74, 12 X 12 MM, MO-192ABD-1, CSPBGA-74
AD5516ABCZ-1	ADI	获取价格	16-Channel 12-Bit Bipolar Voltage-Output DAC with 14-Bit Increment Mode
AD5516ABCZ-2	ROCHESTER	获取价格	SERIAL INPUT LOADING, 14-BIT DAC, PBGA74, 12 X 12 MM, MO-192ABD-1, CSPBGA-74

与AD5516_03相关文章

压敏电阻器在直流电路中的过压保护应用探讨
2024-06-07

10
电感耐压值及其与电感大小的关系
2024-06-07

14
CNY17F光耦合器：特性、应用、封装、引脚功能及替换型号解析
2024-06-07

17
DS1307资料解析：特性、引脚说明、替代推荐
2024-06-07

10

产品中心

服务支持

精选活动

关于我们

帮助中心

AD5516_03

AD5516_03 数据手册

与AD5516_03相关器件

与AD5516_03相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AD5516_03

AD5516_03 数据手册

与AD5516_03相关器件

与AD5516_03相关文章

您还可以找

您在本页遇到什么问题？