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AD5372

更新时间: 2024-01-21 04:35:39
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
25页 301K
描述
32-Channel, 16/14, Serial Input, Voltage-Output DACs

AD5372 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:LFQFP,针数:64
Reach Compliance Code:unknown风险等级:5.77
最大模拟输出电压:15.1 V最小模拟输出电压:-3.1 V
转换器类型:D/A CONVERTER输入位码:BINARY
输入格式:SERIALJESD-30 代码:S-PQFP-G64
JESD-609代码:e3长度:10 mm
最大线性误差 (EL):0.0061%湿度敏感等级:3
标称负供电电压:-15 V位数:16
功能数量:1端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260认证状态:COMMERCIAL
座面最大高度:1.6 mm标称安定时间 (tstl):20 µs
标称供电电压:15 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:10 mmBase Number Matches:1

AD5372 数据手册

 浏览型号AD5372的Datasheet PDF文件第1页浏览型号AD5372的Datasheet PDF文件第2页浏览型号AD5372的Datasheet PDF文件第3页浏览型号AD5372的Datasheet PDF文件第5页浏览型号AD5372的Datasheet PDF文件第6页浏览型号AD5372的Datasheet PDF文件第7页 
AD5372/AD5373  
SPECIFICATIONS  
Preliminary Technical Data  
DVCC = 2.3 V to 5.5 V; VDD = 8 V to 16.5 V; VSS = −4.5 V to −16.5 V; VREF = 3 V; AGND = DGND = SIGGND = 0 V; RL = Open Circuit;  
Gain (m), Offset(c) and DAC Offset registers at default value; all specifications TMIN to TMAX, unless otherwise noted.  
Table 2. Performance Specifications  
Parameter  
AD53721  
B Version  
AD53731  
B Version  
Unit  
Test Conditions/Comments2  
ACCURACY  
Resolution  
16  
4
1
20  
20  
100  
100  
35  
14  
1
1
20  
20  
100  
100  
35  
Bits  
Relative Accuracy  
Differential Nonlinearity  
Offset Error  
LSB max  
LSB max  
mV max  
mV max  
µV max  
µV max  
mV  
Guaranteed monotonic by design over temperature.  
Before Calibration  
Before Calibration  
After Calibration  
After Calibration  
Gain Error  
Offset Error2  
Gain Error2  
Gain Error of Offset DAC  
Positive or Negative Full Scale. See Offset DACs  
section for details  
VOUT Temperature Coefficient  
DC Crosstalk2  
5
5
ppm FSR/°C Includes linearity, offset, and gain drift.  
typ  
0.5  
0.5  
mV max  
Typically 100 µV. Measured channel at mid-scale, full-  
scale change on any other channel  
REFERENCE INPUTS (VREF1, VREF2)2  
VREF DC Input Impedance  
VREF Input Current  
1
60  
2/5  
1
60  
2/5  
MΩ min  
nA max  
V min/max  
Typically 100 MΩ.  
Per input. Typically 30 nA.  
2ꢀ for specified operation.  
VREF Range  
SIGGND INPUT (SIGGND0 TO SIGGND4)2  
DC Input Impedance  
55  
55  
kΩ min  
Typically 60 kΩ.  
Input Range  
0.5  
0.5  
V min/max  
OUTPUT CHARACTERISTICS2  
Output Voltage Range  
VSS + 1.4  
VDD − 1.4  
VSS + 1.4  
VDD − `.4  
V min  
V max  
ILOAD = 1 mA.  
ILOAD = 1 mA.  
Short Circuit Current  
Load Current  
Capacitive Load  
DC Output Impedance  
DIGITAL INPUTS  
5
5
mA max  
mA max  
pF max  
Ω max  
1
1
2200  
1
2200  
1
JEDEC compliant.  
Input High Voltage  
1.7  
2.0  
0.8  
8
1.7  
2.0  
0.8  
8
V min  
V min  
V max  
µA max  
IOVCC = 2.5 V to 3.6 V.  
IOVCC = 3.6 V to 5.5 V.  
IOVCC = 2.5 V to 5.5 V.  
CLR and RESET pin only.  
Input Low Voltage  
Input Current (with pull-up/pull-  
down)  
Input Current (no pull-up/pull-down)  
Input Capacitance2  
1
10  
1
10  
µA max  
pF max  
All other digital input pins.  
DIGITAL OUTPUTS (SDO)  
Output Low Voltage  
Output High Voltage (SDO)  
High Impedance Leakage Current  
High Impedance Output Capacitance2 10  
0.5  
DVCC − 0.5  
−5  
0.5  
DVCC − 0.5  
−5  
10  
V max  
V min  
µA max  
pF typ  
Sinking 200 µA.  
Sourcing 200 µA.  
SDO only.  
Rev. PrF| Page 4 of 25  

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