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AD53500JRP PDF预览

AD53500JRP

更新时间: 2024-09-16 22:32:55
品牌 Logo 应用领域
亚德诺 - ADI 驱动器
页数 文件大小 规格书
7页 104K
描述
High Speed, High Current Capability Pin Driver

AD53500JRP 数据手册

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High Speed, High Current  
Capability Pin Driver  
a
AD53500  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
–2 V to +6 V Output Range  
2.5 Output Resistance  
2.5 ns Tr/Tf for a 3 V Step  
300 MHz Toggle Rate  
V
V
V
EE  
CC  
CC  
V
EE  
39nF  
39nF  
Can Drive 25 Lines and Lower  
Peak Dynamic Current Capability of 400 mA  
Inhibit Leakage <1 A  
V
H
V
DATA  
HDCPL  
2  
DATA  
INH  
On-Chip Temperature Sensor  
DRIVER  
V
OUT  
INH  
APPLICATIONS  
V
L
V
Automatic Test Equipment  
Semiconductor Test Systems  
Board Test Systems  
LDCPL  
TV  
CC  
AD53500  
Instrumentation and Characterization Equipment  
THERM  
1.0A/K  
GND  
GND  
GND  
GND  
GND  
PRODUCT DESCRIPTION:  
of less than 10 ns with a 1000 pF capacitance. To test I/O  
The AD53500 is a complete high speed driver designed for use  
in digital or mixed signal test systems where high speed and high  
output drive capabilities are needed. Combining a high speed  
monolithic process and a unique surface mount package, this  
product attains superb electrical performance while preserving  
optimum packing densities and long-term reliability thanks to an  
ultrasmall 20-lead, PSOP package with built-in heat sink.  
devices, the pin driver can be switched into a high impedance  
state (Inhibit Mode), electrically removing the driver from the  
path. The pin driver leakage current in inhibit is typically less  
than 1 µA and output capacitance is typically less than 18 pF.  
Transitions from HI/LO or to inhibit are controlled through the  
data and inhibit inputs. The input circuitry utilizes high-speed  
differential inputs with a common-mode range of –2 V to +5 V.  
This allows for direct interface to the precision of differential  
ECL timing or the simplicity of stimulating the pin driver from a  
single-ended CMOS or TTL logic source or any combination  
over the common-mode range. The analog logic HI/LO inputs  
are equally easy to interface, typically requiring 50 µA of bias  
current.  
High and low reference levels can be set within a –2 V to +6 V  
range with low offset voltage and high gain accuracy. A 2.5 Ω  
output resistance allows use of an external backmatch resistor for  
application to 50 , 25 or other complex impedance load  
requirements. Without a backmatch resistor it is also capable of  
driving highly capacitive loads, typically achieving a rise/fall time  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 1999  

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