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AD5360BCPZ1

更新时间： 2024-11-24 12:27:55
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
28页 825K
描述
16-Channel, 16-/14-Bit, Serial Input, Voltage-Output DAC

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AD5360BCPZ1 数据手册

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16-Channel, 16-/14-Bit,  
Serial Input, Voltage-Output DAC  
AD5360/AD5361  
SPI-compatible serial interface  
FEATURES  
2.5 V to 5.5 V digital interface  
16-channel DAC in 52-lead LQFP and 56-lead LFCSP  
packages  
RESET  
Digital reset (  
)
Clear function to user-defined SIGGNDx  
Simultaneous update of DAC outputs  
Guaranteed monotonic to 16/14 bits  
Nominal output voltage range of −10 V to +10 V  
Multiple output spans available  
Temperature monitoring function  
Channel monitoring multiplexer  
GPIO function  
System calibration function allowing user-programmable  
offset and gain  
Channel grouping and addressing features  
Data error checking feature  
APPLICATIONS  
Instrumentation  
Industrial control systems  
Level setting in automatic test equipment (ATE)  
Variable optical attenuators (VOA)  
Optical line cards  
FUNCTIONAL BLOCK DIAGRAM  
DVCC  
VDD  
VSS  
AGND DGND  
LDAC  
TEMP  
VREF0  
TEMP_OUT  
PEC  
n = 16 FOR AD5360  
n = 14 FOR AD5361  
SENSOR  
GROUP 0  
BUFFER  
8
CONTROL  
REGISTER  
14  
n
14  
n
OFFSET  
DAC 0  
OFS0  
REGISTER  
VOUT0 TO  
VOUT15  
8
n
8
A/B SELECT  
REGISTER  
TO  
MON_IN0  
MON_IN1  
BUFFER  
MUX 2s  
6
OUTPUT BUFFER  
AND POWER-  
DOWN CONTROL  
VOUT0  
VOUT1  
VOUT2  
VOUT3  
VOUT4  
VOUT5  
VOUT6  
VOUT7  
n
X2A REGISTER  
X2B REGISTER  
DAC 0  
REGISTER  
MUX  
n
A/B  
MUX  
MUX  
2
DAC 0  
X1 REGISTER  
n
n
n
·
·
·
·
·
·
·
·
·
·
·
·
M REGISTER  
C REGISTER  
·
·
·
·
·
·
MON_OUT  
n
n
n
·
·
·
·
·
·
·
·
·
2
GPIO  
REGISTER  
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
GPIO  
BIN/2SCOMP  
·
OUTPUT BUFFER  
AND POWER-  
n
n
n
X2A REGISTER  
n
n
A/B  
MUX  
2
DAC 7  
SYNC  
SDI  
X1 REGISTER  
DOWN CONTROL  
DAC 7  
MUX  
REGISTER  
SIGGND0  
VREF1  
X2B REGISTER  
n
n
n
SERIAL  
INTERFACE  
M REGISTER  
C REGISTER  
SCLK  
SDO  
GROUP 1  
14  
n
n
n
OFFSET  
DAC 1  
OFS1  
REGISTER  
BUSY  
8
8
TO  
MUX 2s  
A/B SELECT  
REGISTER  
BUFFER  
RESET  
CLR  
OUTPUT BUFFER  
AND POWER-  
DOWN CONTROL  
VOUT8  
n
n
X2A REGISTER  
DAC 0  
REGISTER  
n
A/B  
MUX  
MUX  
2
DAC 0  
X1 REGISTER  
VOUT9  
X2B REGISTER  
n
n
n
VOUT10  
VOUT11  
VOUT12  
VOUT13  
VOUT14  
VOUT15  
·
·
·
·
·
·
·
·
·
·
·
·
·
M REGISTER  
C REGISTER  
·
·
·
·
·
·
STATE  
MACHINE  
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
n
·
OUTPUT BUFFER  
AND POWER-  
n
n
n
n
X2A REGISTER  
n
DAC 7  
A/B  
MUX  
2
X1 REGISTER  
DAC 7  
DOWN CONTROL  
REGISTER  
MUX  
SIGGND1  
X2B REGISTER  
AD5360/  
AD5361  
n
n
n
M REGISTER  
C REGISTER  
n
Figure 1.  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 www.analog.com  
Fax: 781.461.3113 ©2007–2008 Analog Devices, Inc. All rights reserved.  
 
 
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