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AD5360

更新时间： 2024-09-18 04:30:39
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亚德诺 - ADI /
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25页 278K
描述
16-Channel, 16/14-Bit, Serial Input, Voltage-Output DAC

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AD5360 数据手册

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16-Channel, 16/14-Bit,  
Serial Input, Voltage-Output DAC  
Preliminary Technical Data  
AD5360/AD5361  
SPI compatible serial interface  
2.5 V to 5.5 V digital interface  
Power-on reset  
FEATURES  
16-channel DAC in 52-LQFP and 56-LFCSP  
Guaranteed monotonic to 16/14 bits  
Nominal output voltage range of -10 V to +10 V  
Multiple output spans available  
Temperature Monitoring Function  
Channel Monitoring Multiplexer  
GPIO Function  
System calibration function allowing user-programmable  
offset and gain  
Channel grouping and addressing features  
Data error checking feature  
Digital reset (RESET)  
Clear function to user-defined SIGGND (CLR pin)  
Simultaneous update of DAC outputs (LDAC pin)  
APPLICATIONS  
Instrumentation  
Industrial control systems  
Level setting in automatic test equipment (ATE)  
Variable optical attenuators (VOA)  
Optical Line Cards  
FUNCTIONAL BLOCK DIAGRAM  
DVCC  
VDD  
VSS  
AGND DNGD  
LDAC  
VREF0  
TEMP  
SENSOR  
AD5360, n = 16  
AD5361, n = 14  
TEMP_OUT  
PEC  
GROUP 0  
BUFFER  
14  
n
8
14  
n
OFFSET  
DAC 0  
OFS0  
REGISTER  
CONTROL  
REGISTER  
8
8
A/B SELECT  
TO  
MUX 2's  
BUFFER  
REGISTER  
MON_IN0  
MON_IN1  
VOUT0 -  
VOUT15  
OUTPUT BUFFER  
AND POWER  
DOWN CONTROL  
n
VOUT0  
VOUT1  
VOUT2  
VOUT3  
VOUT4  
VOUT5  
VOUT6  
VOUT7  
n
n
X1A REGISTER  
X2A REGISTER  
DAC 0  
REGISTER  
MUX  
2
MUX  
1
DAC 0  
n
n
6
2
X2B REGISTER  
X1B REGISTER  
M REGISTER  
C REGISTER  
n
MUX  
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
n
n
MON_OUT  
GPIO  
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
GPIO  
REGISTER  
BIN/2SCOMP  
SYNC  
SDI  
OUTPUT BUFFER  
AND POWER  
·
n
n
n
n
n
n
X1A REGISTER  
X2A REGISTER  
DAC 7  
MUX  
2
MUX  
1
DAC 7  
DOWN CONTROL  
n
n
SIGGND0  
REGISTER  
X2B REGISTER  
X1B REGISTER  
M REGISTER  
C REGISTER  
SERIAL  
INTERFACE  
n
SCLK  
n
VREF1  
GROUP 1  
SDO  
14  
n
14  
n
OFFSET  
DAC 1  
OFS1  
REGISTER  
BUSY  
8
8
TO  
MUX 2's  
A/B SELECT  
REGISTER  
BUFFER  
RESET  
CLR  
OUTPUT BUFFER  
AND POWER  
DOWN CONTROL  
n
VOUT8  
n
n
n
X1A REGISTER  
X2A REGISTER  
DAC 0  
REGISTER  
MUX  
2
MUX  
1
DAC 0  
VOUT9  
n
n
X2B REGISTER  
X1B REGISTER  
M REGISTER  
C REGISTER  
VOUT10  
VOUT11  
VOUT12  
VOUT13  
VOUT14  
VOUT15  
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
STATE  
MACHINE  
n
n
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
n
OUTPUT BUFFER  
AND POWER  
·
n
n
n
n
n
n
POWER-ON  
RESET  
X1A REGISTER  
X2A REGISTER  
DAC 7  
MUX  
2
MUX  
1
DAC 7  
DOWN CONTROL  
n
n
SIGGND1  
REGISTER  
X2B REGISTER  
X1B REGISTER  
M REGISTER  
C REGISTER  
5360-0001  
n
AD5360/  
AD5361  
n
Figure 1.  
AD5360/AD5361—Protected by U.S. Patent No. 5,969,657; other patents pending  
Rev. PrF  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective companies.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2006 Analog Devices, Inc. All rights reserved.  
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