Datasheet > AD5341BRUZ-REEL71

AD5341BRUZ-REEL71

更新时间： 2022-04-12 22:44:08

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
28页	542K
描述
2.5 V to 5.5 V, 115 Î¼A, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs

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AD5341BRUZ-REEL71 数据手册

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AD5330/AD5331/AD5340/AD5341

REF

POWER-ON

RESET

AD5340

BUF

DAC

INPUT

GAIN 10

12-BIT

DAC

BUF

BUFFER

OUT

DB 24

REF

OUT

12-BIT

AD5340

TOP VIEW

CLR

(Not to Scale)

GND

RESET

POWER-DOWN

LOGIC

17 DB

16 DB

15 DB

LDAC

GAIN

CLR

LDAC

PD GND

Figure 7. AD5340 Functional Block Diagram

Figure 8. AD5340 Pin Configuration

Table 7. AD5340 Pin Function Descriptions

Pin No.

Mnemonic

DB_ꢀ0

DB_ꢀꢀ

Description

ꢀ

Parallel Data Input.

Most Significant Bit of Parallel Data Input.

BUF

Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.

V_REF

Reference Input.

V_OUT

Output of DAC. Buffered output with rail-to-rail operation.

No Connect.

Ground reference point for all circuitry on the part.

GND

Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.

Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.

ꢀ0

ꢀꢀ

ꢀ2

ꢀ3

ꢀ4

GAIN

CLR

LDAC

Gain Control Pin. This controls whether the output range from the DAC is 0 V to V_REFor 0 V to 2 × V_REF

Asynchronous active low control input that clears all input registers and DAC registers to zero.

Active low control input that updates the DAC registers with the contents of the input registers.

Power-Down Pin. This active low control pin puts the DAC into power-down mode.

V_DD

Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a

ꢀ0 μF capacitor in parallel with a 0.ꢀ μF capacitor to GND.

ꢀ5 to 24 DB₀to DB₉

Ten Parallel Data Inputs.

Rev. A | Page 9 of 28

1...6 7 8910 11 12...28

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