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AD5341BRUZ-REEL71 PDF预览

AD5341BRUZ-REEL71

更新时间: 2022-04-12 22:44:08
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
28页 542K
描述
2.5 V to 5.5 V, 115 μA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs

AD5341BRUZ-REEL71 数据手册

 浏览型号AD5341BRUZ-REEL71的Datasheet PDF文件第4页浏览型号AD5341BRUZ-REEL71的Datasheet PDF文件第5页浏览型号AD5341BRUZ-REEL71的Datasheet PDF文件第6页浏览型号AD5341BRUZ-REEL71的Datasheet PDF文件第8页浏览型号AD5341BRUZ-REEL71的Datasheet PDF文件第9页浏览型号AD5341BRUZ-REEL71的Datasheet PDF文件第10页 
AD5330/AD5331/AD5340/AD5341  
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
V
V
DD  
REF  
3
12  
POWER-ON  
RESET  
AD5330  
BUF  
1
8
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
BUF  
NC  
DB  
DB  
DB  
DB  
DB  
DB  
DB  
DB  
7
6
DAC  
REGISTER  
INPUT  
REGISTER  
GAIN  
8-BIT  
DAC  
DB 20  
4
BUFFER  
7
0
V
OUT  
.
.
V
3
REF  
OUT  
5
13  
DB  
8-BIT  
AD5330  
TOP VIEW  
V
4
4
6
CS  
5
GND  
CS  
3
(Not to Scale)  
7
6
WR  
CLR  
2
RESET  
7
WR  
POWER-DOWN  
LOGIC  
1
9
8
GAIN  
CLR  
LDAC  
0
10  
LDAC  
9
V
DD  
10  
PD  
11  
5
PD GND  
NC = NO CONNECT  
Figure 3. AD5330 Functional Block Diagram  
Figure 4. AD5330 Pin Configuration  
Table 5. AD5330 Pin Function Descriptions  
Pin No.  
Mnemonic  
BUF  
NC  
Description  
2
Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.  
No Connect.  
3
VREF  
Reference Input.  
4
5
VOUT  
GND  
CS  
Output of DAC. Buffered output with rail-to-rail operation.  
Ground reference point for all circuitry on the part.  
1
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.  
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.  
7
WR  
8
9
GAIN  
CLR  
Gain Control Pin. This controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF  
Asynchronous active low control input that clears all input registers and DAC registers to zero.  
Active low control input that updates the DAC registers with the contents of the input registers.  
Power-Down Pin. This active low control pin puts the DAC into power-down mode.  
.
ꢀ0  
ꢀꢀ  
ꢀ2  
LDAC  
PD  
VDD  
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a  
ꢀ0 μF capacitor in parallel with a 0.ꢀ μF capacitor to GND.  
ꢀ3 to 20  
DB0 to DB7  
Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.  
Rev. A | Page 7 of 28  
 

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