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AD5330 PDF预览

AD5330

更新时间: 2024-09-20 22:53:27
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
20页 352K
描述
2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs

AD5330 数据手册

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AD5330/AD5331/AD5340/AD5341  
AD5330 FUNCTIONAL BLOCK DIAGRAM  
AD5330 PIN CONFIGURATION  
V
V
DD  
REF  
1
2
20  
19  
18  
DB  
BUF  
NC  
7
DB  
DB  
POWER-ON  
RESET  
6
AD5330  
3
V
REF  
OUT  
5
4
3
4
17 DB  
16 DB  
V
BUF  
8-BIT  
5
GND  
CS  
DAC  
REGISTER  
INPUT  
REGISTER  
AD5330  
GAIN  
TOP VIEW  
8-BIT  
DAC  
6
15  
DB  
DB  
V
2
BUFFER  
7
.
OUT  
(Not to Scale)  
.
INTER-  
FACE  
LOGIC  
DB  
0
7
14 DB  
13 DB  
WR  
1
8
GAIN  
CLR  
LDAC  
0
CS  
9
12  
11  
V
DD  
WR  
CLR  
10  
PD  
RESET  
POWER-DOWN  
LOGIC  
NC = NO CONNECT  
LDAC  
GND  
PD  
AD5330 PIN FUNCTION DESCRIPTIONS  
Pin  
No.  
Mnemonic  
Function  
1
2
BUF  
NC  
Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.  
No Connect.  
3
4
5
6
7
8
9
10  
11  
12  
VREF  
VOUT  
GND  
CS  
Reference Input.  
Output of DAC. Buffered output with rail-to-rail operation.  
Ground reference point for all circuitry on the part.  
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.  
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.  
Gain Control Pin. This controls whether the output range from the DAC is 0–VREF or 0–2 VREF.  
Asynchronous active low control input that clears all input registers and DAC registers to zero.  
Active low control input that updates the DAC registers with the contents of the input registers.  
Power-Down Pin. This active low control pin puts the DAC into power-down mode.  
WR  
GAIN  
CLR  
LDAC  
PD  
VDD  
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled  
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.  
13–20  
DB0–DB7  
Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.  
–5–  
REV. 0  

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