AD5330

更新时间： 2024-09-18 22:53:27

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
20页	352K
描述
2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs

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中文翻译

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数据手册

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AD5330 数据手册

AD5330/AD5331/AD5340/AD5341

(V_DD= 2.5 V to 5.5 V. R_L= 2 k⍀ to GND; C_L= 200 pF to GND; all speciﬁcations T_MINto T_MAX

unless otherwise noted.)

AC CHARACTERISTICS¹

B Version³

Parameter²

Min

Typ

Max

Unit

Conditions/Comments

_REF= 2 V. See Figure 20

Output Voltage Settling Time

AD5330

AD5331

AD5340

AD5341

0.7

0.5

200

–70

µs

1/4 Scale to 3/4 Scale Change (40 H to C0 H)

1/4 Scale to 3/4 Scale Change (100 H to 300 H)

1/4 Scale to 3/4 Scale Change (400 H to C00 H)

µs

V/µs

nV-s

kHz

Slew Rate

Major Code Transition Glitch Energy

Digital Feedthrough

Multiplying Bandwidth

Total Harmonic Distortion

1 LSB Change Around Major Carry

V_REF= 2 V 0.1 V p-p. Unbuffered Mode

V_REF= 2.5 V 0.1 V p-p. Frequency = 10 kHz

NOTES

¹Guaranteed by design and characterization, not production tested.

²See Terminology section.

³Temperature range: B Version: –40°C to +105°C; typical speciﬁcations are at 25°C.

Speciﬁcations subject to change without notice.

TIMING CHARACTERISTICS^{1, 2, 3}(V_DD= 2.5 V to 5.5 V, All speciﬁcations T_MINto T_MAXunless otherwise noted.)

Parameter

Limit at T_MIN, T_MAX

Unit

Condition/Comments

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

4.5

ns min

CS to WR Setup Time

CS to WR Hold Time

WR Pulsewidth

Data, GAIN, BUF, HBEN Setup Time

Data, GAIN, BUF, HBEN Hold Time

Synchronous Mode. WR Falling to LDAC Falling.

Synchronous Mode. LDAC Falling to WR Rising.

Synchronous Mode. WR Rising to LDAC Rising.

Asynchronous Mode. LDAC Rising to WR Rising.

Asynchronous Mode. WR Rising to LDAC Falling.

LDAC Pulsewidth

t₉

t₁₀

t₁₁

t₁₂

t₁₃

CLR Pulsewidth

Time Between WR Cycles

NOTES

¹Guaranteed by design and characterization, not production tested.

²All input signals are specified with tr = tf = 5 ns (10% to 90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

³See Figure 1.

t₂

t₁

t₁₃

t₃

t₅

t₄

DATA,

GAIN,

BUF,

HBEN

t₈

t₆

t₇

t₉

LDAC

t₁₀

t₁₁

LDAC

t₁₂

CLR

NOTES:

SYNCHRONOUS LDAC UPDATE MODE

ASYNCHRONOUS LDAC UPDATE MODE

Figure 1. Parallel Interface Timing Diagram

–3–

REV. 0

1 234 5 6 7...20

中文翻译

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与AD5330相关器件

型号	品牌	获取价格	描述	数据表
AD5330_08	ADI	获取价格	2.5 V to 5.5 V, 115 Î¼A, Parallel Interface S
AD5330BRU	ADI	获取价格	2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs
AD5330BRU-REEL	ADI	获取价格	2.5 V to 5.5 V, 115 Î¼A, Parallel Interface S
AD5330BRU-REEL7	ADI	获取价格	2.5 V to 5.5 V, 115 Î¼A, Parallel Interface S
AD5330BRUZ	ADI	获取价格	2.5V to 5.5V, 115µA Parallel Interface Single Voltage-Output 8-Bit DAC
AD5330BRUZ	ROCHESTER	获取价格	PARALLEL, 8 BITS INPUT LOADING, 6 us SETTLING TIME, 8-BIT DAC, PDSO20, PLASTIC, TSSOP-20
AD5330BRUZ1	ADI	获取价格	2.5 V to 5.5 V, 115 Î¼A, Parallel Interface S
AD5330BRUZ-REEL	ADI	获取价格	暂无描述
AD5330BRUZ-REEL1	ADI	获取价格	2.5 V to 5.5 V, 115 Î¼A, Parallel Interface S
AD5330BRUZ-REEL7	ADI	获取价格	2.5V to 5.5V, 115µA Parallel Interface Single Voltage-Output 8-Bit DAC

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