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AD5270BRMZ-50-RL7 PDF预览

AD5270BRMZ-50-RL7

更新时间： 2024-09-17 12:27:27
品牌 Logo 应用领域
亚德诺 - ADI 转换器电位器数字电位计存储电阻器光电二极管
页数 文件大小 规格书
24页 725K
描述
1024-/256-Position, 1% Resistor Tolerance Error, SPI Interface and 50-TP Memory Digital Rheostat

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AD5270BRMZ-50-RL7 数据手册

 浏览型号AD5270BRMZ-50-RL7的Datasheet PDF文件第7页浏览型号AD5270BRMZ-50-RL7的Datasheet PDF文件第8页浏览型号AD5270BRMZ-50-RL7的Datasheet PDF文件第9页浏览型号AD5270BRMZ-50-RL7的Datasheet PDF文件第11页浏览型号AD5270BRMZ-50-RL7的Datasheet PDF文件第12页浏览型号AD5270BRMZ-50-RL7的Datasheet PDF文件第13页 
AD5270/AD5271  
Data Sheet  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
10  
9
V
1
2
3
4
5
SYNC  
DD  
A
SCLK  
DIN  
AD5270/  
AD5271  
(EXPOSED  
PAD)  
8
W
V
7
SDO  
GND  
SS  
V
1
2
3
4
5
10  
9
SYNC  
SCLK  
DIN  
DD  
A
AD5270/  
AD5271  
6
EXT_CAP  
8
W
TOP VIEW  
V
7
NOTES  
SS  
EXT_CAP  
SDO  
GND  
(Not to Scale)  
1. THE EXPOSED PAD IS LEFT FLOATING  
OR IS TIED TO V  
6
.
SS  
Figure 6. LFCSP Pin Configuration  
Figure 5. MSOP Pin Configuration  
Table 10. Pin Function Descriptions  
Pin No.  
Mnemonic  
Description  
1
2
3
4
VDD  
A
W
Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors.  
Terminal A of RDAC. VSS ≤ VA ≤ VDD.  
Wiper Terminal of RDAC. VSS ≤ VW ≤ VDD.  
Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 μF ceramic  
capacitors and 10 μF capacitors.  
VSS  
5
EXT_CAP  
External Capacitor. Connect a 1 μF capacitor between EXT_CAP and VSS. This capacitor must have a voltage  
rating of ≥7 V.  
6
7
GND  
SDO  
Ground Pin, Logic Ground Reference.  
Serial Data Output. This pin can be used to clock data from the shift register in daisy-chain mode or in  
readback mode. This open-drain output requires an external pull-up resistor even if it is not use.  
8
DIN  
Serial Data Line. This pin is used in conjunction with the SCLK line to clock data into or out of the 16-bit input  
register.  
9
SCLK  
SYNC  
Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can  
be transferred at rates up to 50 MHz.  
10  
Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC  
goes low, it enables the shift register and data is transferred in on the falling edges of the subsequent clocks.  
The selected register is updated on the rising edge of SYNC following the 16th clock cycle. If SYNC is taken  
high before the 16th clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is  
ignored by the RDAC.  
EPAD  
Exposed Pad  
Leave floating or connected to VSS.  
Rev. F | Page 10 of 24  
 
1...78910111213...24

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AD5270BRMZ-50-RL7 替代型号

型号 品牌 替代类型 描述 数据表
AD5270BRMZ-50 ADI

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 1024-/256-Position, 1% Resistor Tolerance Error, SPI Interface and 50-TP Memory Digital Rh

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