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A3P600L-FG144I PDF预览

A3P600L-FG144I

更新时间： 2024-11-19 19:31:39
品牌 Logo 应用领域
ACTEL 时钟栅可编程逻辑
页数 文件大小 规格书
224页 7287K
描述
Field Programmable Gate Array, 13824 CLBs, 600000 Gates, 350MHz, 13824-Cell, CMOS, PBGA144, 13 X 13 MM, 1.45 MM HEIGHT, 1 MM PITCH, FBGA-144

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A3P600L-FG144I 技术参数

是否Rohs认证：不符合生命周期：Transferred
包装说明：13 X 13 MM, 1.45 MM HEIGHT, 1 MM PITCH, FBGA-144Reach Compliance Code：compliant
风险等级：5.81Is Samacsys：N
最大时钟频率：350 MHzJESD-30 代码：S-PBGA-B144
JESD-609代码：e0长度：13 mm
湿度敏感等级：3可配置逻辑块数量：13824
等效关口数量：600000输入次数：97
逻辑单元数量：13824输出次数：97
端子数量：144最高工作温度：85 °C
最低工作温度：-40 °C组织：13824 CLBS, 600000 GATES
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：BGA144,12X12,40封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE峰值回流温度（摄氏度）：225
电源：1.5/3.3 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：1.55 mm
子类别：Field Programmable Gate Arrays最大供电电压：1.575 V
最小供电电压：1.14 V标称供电电压：1.2 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN LEAD SILVER
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：13 mmBase Number Matches：1

A3P600L-FG144I 数据手册

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Revision 9  
®
ProASIC3L Low Power Flash FPGAs  
with Flash*Freeze Technology  
Features and Benefits  
•
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /  
2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and  
LVCMOS 2.5 V / 5.0 V Input  
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and  
M-LVDS  
Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL  
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3  
Class I and II (A3PE3000L only)  
Wide Range Power Supply Voltage Support per JESD8-B,  
Allowing I/Os to Operate from 2.7 V to 3.6 V  
Wide Range Power Supply Voltage Support per JESD8-12,  
Allowing I/Os to Operate from 1.14 V to 1.575 V  
I/O Registers on Input, Output, and Enable Paths  
Hot-Swappable and Cold-Sparing I/Os Programmable Output  
Slew Rate and Drive Strength  
Low Power  
•
•
•
•
•
Dramatic Reduction in Dynamic and Static Power Savings  
1.2 V to 1.5 V Core and I/O Voltage Support for Low Power  
Low Power Consumption in Flash*Freeze Mode Allows for  
Instantaneous Entry to / Exit from Low-Power Flash*Freeze  
Mode  
•
•
•
•
Supports Single-Voltage System Operation  
Low-Impedance Switches  
High Capacity  
•
•
•
250,000 to 3,000,000 System Gates  
Up to 504 kbits of True Dual-Port SRAM  
Up to 620 User I/Os  
•
•
Reprogrammable Flash Technology  
•
•
•
•
•
Programmable Input Delay (A3PE3000L only)  
Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L)  
Weak Pull-Up/-Down  
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS  
Process  
•
•
•
Live-at-Power-Up (LAPU) Level 0 Support  
Single-Chip Solution  
IEEE 1149.1 (JTAG) Boundary Scan Test  
®
Pin-Compatible Packages across the ProASIC 3L Family  
Retains Programmed Design when Powered Off  
(except PQ208)  
High Performance  
Clock Conditioning Circuit (CCC) and PLL  
•
350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System  
Performance  
3.3 V, 66 MHz, 66-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit  
PCI (1.2 V systems)  
•
•
•
Six CCC Blocks, One with Integrated PLL (ProASIC3L) and All  
with Integrated PLL (ProASIC3EL)  
Configurable Phase Shift, Multiply/Divide, Delay Capabilities,  
and External Feedback  
Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V  
systems) and 350 MHz (1.5 V systems))  
•
In-System Programming (ISP) and Security  
•
Secure ISP Using On-Chip 128-Bit Advanced Encryption  
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)  
SRAMs and FIFOs  
®
•
FlashLock to Secure FPGA Contents  
•
Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,  
and ×18 organizations available)  
High-Performance Routing Hierarchy  
•
•
True Dual-Port SRAM (except ×18)  
24 SRAM and FIFO Configurations with Synchronous  
Operation:  
•
•
•
Segmented, Hierarchical Routing and Clock Structure  
High-Performance, Low-Skew Global Network  
Architecture Supports Ultra-High Utilization  
– 250 MHz: For 1.2 V systems  
Advanced and Pro (Professional) I/Os  
– 350 MHz: For 1.5 V systems  
•
•
•
700 Mbps DDR, LVDS-Capable I/Os  
1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation  
Bank-Selectable I/O Voltages—up to 8 Banks per Chip  
ARM® Processor Support in ProASIC3L FPGAs  
•
ARM Cortex™-M1 Soft Processor Available with or without  
Debug  
Table 1 • ProASIC3 Low-Power Product Family  
ProASIC3L Devices  
ARM Cortex-M1 Devices  
System Gates  
A3P250L  
A3P600L  
A3P1000L  
A3PE3000L  
1
M1A3P600L  
M1A3P1000L  
M1A3PE3000L  
250,000  
600,000  
13,824  
108  
24  
1,000,000  
3,000,000  
VersaTiles (D-flip-flops)  
RAM Kbits (1,024 bits)  
4,608-Bit Blocks  
6,144  
36  
8
24,576  
144  
32  
75,264  
504  
112  
1
FlashROM Kbits  
1
1
1
2
Secure (AES) ISP  
Yes  
1
Yes  
1
Yes  
1
Yes  
6
3
Integrated PLL in CCCs  
VersaNet Globals  
I/O Banks  
18  
4
18  
18  
18  
4
4
8
Maximum User I/Os  
157  
235  
300  
620  
Package Pins  
VQFP  
VQ100  
PQ208  
FG144, FG256  
3
PQFP  
PQ208  
FG144, FG256, FG484  
PQ208  
FG144, FG256, FG484  
PQ208  
FBGA  
FG324, FG484, FG896  
Notes:  
1. Refer to the Cortex-M1 product brief for more information.  
2. AES is not available for ARM Cortex-M1 ProASIC3L devices.  
3. For the A3PE3000L, the PQ208 package has six CCCs and two PLLs.  
February 2009  
I
© 2010 Actel Corporation  
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