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A1K-L67130L-70 PDF预览

A1K-L67130L-70

更新时间: 2022-12-01 21:13:36
品牌 Logo 应用领域
TEMIC 静态存储器
页数 文件大小 规格书
16页 196K
描述
Dual-Port SRAM, 1KX8, 70ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48

A1K-L67130L-70 数据手册

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L67130/L67140  
(5)  
Table 2 : Arbitration  
LEFT PORT  
RIGHT PORT  
FLAGS  
FUNCTION  
CSL  
H
A0L – A9L  
CSR  
A0L – A9R  
BUSYL  
BUSYR  
X
Any  
X
H
H
L
L
X
X
H
H
H
H
H
H
H
H
No Contention  
L
No Contention  
No Contention  
No Contention  
H
Any  
L
A – A  
A – A  
0L 9L  
0R  
9R  
ADDRESS ARBITRATION WITH CE LOW BEFORE ADDRESS MATCH  
L
L
L
L
LV5R  
RV5L  
Same  
Same  
L
L
L
L
LV5R  
RV5L  
Same  
Same  
H
L
H
L
L
H
L
L–Port Wins  
R–Port Wins  
Arbitration Resolved  
Arbitration Resolved  
H
CS ARBITRATION WITH ADDRESS MATCH BEFORE CS  
LL5R  
RL5L  
LW5R  
LW5R  
= A – A  
LL5R  
RL5L  
LW5R  
LW5R  
= A – A  
9L  
H
L
H
L
L
H
L
L–Port Wins  
0R  
9R  
9R  
0L  
= A – A  
= A  
A
R–Port Wins  
0R  
0L – 9L  
= A  
A
= A – A  
Arbitration Resolved  
Arbitration Resolved  
0R – 9R  
0L  
9L  
= A – A  
= A – A  
H
0R  
9R  
0L  
9L  
Notes : 5. INT Flags Don’t Care.  
6. X = DON’T CARE, L = LOW, H = HIGH.  
LV5R = Left Address Valid 5 ns before right address.  
RV5L = Right address Valid 5 ns before left address.  
Same = Left and Right Addresses match within 5 ns of each other.  
LL5R = Left CS = LOW 5 ns before Right CS.  
RL5L = Right CS = LOW 5 ns before left CS.  
LW5R = Left and Right CS = LOW within 5 ns of each other.  
(7, 10)  
Table 3 : Interrupt Flag  
LEFT PORT  
RIGHT PORT  
FUNCTION  
R/WL CSL  
OEL  
X
AOL–A9L  
INTL R/WR CSR  
OER  
X
AOR–A9R  
INTR  
(8)  
L
X
X
X
L
X
X
L
3FF  
X
X
X
X
X
L
X
L
L
X
X
L
Set Right INT Flag  
R
(9)  
X
L
3FF  
3FE  
X
H
Reset Right INT Flag  
R
(9)  
X
X
L
X
X
X
Set Left INT Flag  
L
(8)  
L
3FE  
H
X
X
Reset Left INT Flag  
L
Notes : 7. Assumes BUSY = BUSY = H.  
L
R
8. If BUSY = L, then NC.  
L
9. If BUSY = L, then NC.  
R
10. H = HIGH, L = LOW, X = DON’T CARE, NC = NO CHANGE.  
MATRA MHS  
Rev. D (19 Fev. 97)  
5

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