Datasheet > A1K-L67130L-70

A1K-L67130L-70

更新时间： 2022-12-01 21:13:36

品牌	Logo	应用领域
TEMIC		静态存储器
页数	文件大小	规格书
16页	196K
描述
Dual-Port SRAM, 1KX8, 70ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

A1K-L67130L-70 数据手册

L67130/L67140

AC Parameters

L67130–45

L67140–45

L67130–55

L67140–55

L67130–70

L67140–70

READ CYCLE

PARAMETER

UNIT

MIN.

MAX.

MIN.

MAX. MIN. MAX.

SYMBOL

(23)

SYMBOL

(24)

PRELIMINARY

TAVAVR

TAVQV

TELQV

TGLQV

TAVQX

TELQZ

TEHQZ

TPU

Read cycle time

–

Address access time

ACS

AOE

Chip Select access time (22)

Output enable access time

–

Output hold from address change

Output low Z time (20, 21)

Output high Z time (20, 21)

Chip Select to power up time (21)

Chip disable to power down time (21)

–

TPD

–

Notes : 20. Transition is measured ± 500 mV from low or high impedance voltage with load (figures 1 and 2).

21. This parameter is guaranteed but not tested.

22. To access RAM CS = VIL.

23. STD symbol.

24. ALT symbol.

Timing Waveform of Read Cycle n^o1, Either Side ^{(25, 26, 28)}

Timing Waveform of Read Cycle n^o2, Either Side ^{(25, 27, 29)}

Notes : 25. R/W is high for read cycles.

26. Device is continuously enabled, CS = VIL.

27. Addresses valid prior to or coincident with CS transition low.

28. OE = VIL.

29. To access RAM, CS = VIL.

MATRA MHS

Rev. D (19 Fev. 97)

1...5 6 789 10 11...16

中文翻译

下载PDF

与A1K-L67130L-70相关器件

型号	品牌	描述	获取价格	数据表
A1K-L67130V-45	TEMIC	Dual-Port SRAM, 1KX8, 45ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48	获取价格
A1K-L67130V-55	TEMIC	Dual-Port SRAM, 1KX8, 55ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48	获取价格
A1K-L67130V-70	TEMIC	Dual-Port SRAM, 1KX8, 70ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48	获取价格
A1K-L67132L-45	ATMEL	Dual-Port SRAM, 2KX8, 45ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48	获取价格
A1K-L67132L-55	TEMIC	Dual-Port SRAM, 2KX8, 55ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48	获取价格
A1K-L67132L-70	TEMIC	Dual-Port SRAM, 2KX8, 70ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48	获取价格