Datasheet > A1K-L67130L-70

A1K-L67130L-70

更新时间： 2022-12-01 21:13:36

品牌	Logo	应用领域
TEMIC		静态存储器
页数	文件大小	规格书
16页	196K
描述
Dual-Port SRAM, 1KX8, 70ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48

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A1K-L67130L-70 数据手册

L67130/L67140

AC Parameters

L67130–45

L67140–45

L67130–55

L67140–55

L67130–70

L67140–70

WRITE CYCLE

PARAMETER

UNIT

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

SYMBOL SYMBOL

(34)

(35)

PRELIMINARY

TAVAVW

TELWH

TAVWH

TAVWL

TWLWH

TWHAX

TDVWH

TGHQZ

TWHDX

TWLQZ

TWHQX

Write cycle time

–

Chip select to end of write (32)

Address valid to end of write

Address Set–up Time

–

Write Pulse Width

–

Write Recovery Time

–

Data Valid to end of write

Output high Z time (30, 31)

Data hold time (33)

–

Write enable to output in high Z (30, 31)

Output active from end of write (30, 31, 33)

–

Notes : 30. Transition is measured ± 500 mV from low or high impedance voltage with load (figures 1 and 2).

31. This parameter is guaranteed but not tested.

32. To access RAM CS = VIL.

This condition must be valid for entire t time.

33. The specification for t must be met by the device supplying write data to the RAM under all operating conditions.

Although t and t

values vary over voltage and temperature, the actual t will always be smaller than the actual t

34. STD symbol.

35. ALT symbol.

MATRA MHS

Rev. D (19 Fev. 97)

1...6 7 8910 11 12...16

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A1K-L67130V-45	TEMIC	Dual-Port SRAM, 1KX8, 45ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48	获取价格
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A1K-L67132L-70	TEMIC	Dual-Port SRAM, 2KX8, 70ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48	获取价格