Datasheet > A1K-L67130L-70

A1K-L67130L-70

更新时间： 2022-12-01 21:13:36

品牌	Logo	应用领域
TEMIC		静态存储器
页数	文件大小	规格书
16页	196K
描述
Dual-Port SRAM, 1KX8, 70ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48

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A1K-L67130L-70 数据手册

L67130/L67140

Data-Retention Mode

MHS CMOS RAMs are designed with battery backup in 2 – CS must be kept between V – 0.2 V and 70 % of Vcc

mind. Data retention voltage and supply current are during the power up and power down transitions.

guaranteed over temperature. The following rules insure

data retention :

3 – The RAM can begin operation > tRC after Vcc

reaches the minimum operating voltage (3 volts).

1 – Chip select (CS) must be held high during data

retention ; within Vcc to VCC

Timing

MAX

MIL

IND

PARAMETER

TEST CONDITIONS (18)

UNIT

COM

AUTO

ICC

@ VCC = 2 V

µA

DR1

Notes : 18. CS = Vcc, Vin = Gnd to Vcc.

19. = Read cycle time.

AC Test Conditions

Input Pulse Levels : GND to 3.0 V

Input Rise/Fall Times : 5 ns

Output Reference Levels : 1.5 V

Output Load : see figures 1, 2

Input Timing Reference Levels : 1.5 V

Figure 1. Output Load.

Figure 2. Output load.

(For t , t , t , and t

)

HZ LZ WZ

MATRA MHS

Rev. D (19 Fev. 97)

1...4 5 678 9 10...16

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