Datasheet > A1K-L67140V-55

A1K-L67140V-55

更新时间： 2024-12-01 03:01:23

品牌	Logo	应用领域
TEMIC		静态存储器内存集成电路
页数	文件大小	规格书
16页	196K
描述
Dual-Port SRAM, 1KX8, 55ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48

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技术参数
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A1K-L67140V-55 技术参数

生命周期：	Transferred	包装说明：	0.600 INCH, CERAMIC, DIP-48
Reach Compliance Code：	unknown	风险等级：	5.79
最长访问时间：	55 ns	JESD-30 代码：	R-GDIP-T48
内存密度：	8192 bit	内存集成电路类型：	DUAL-PORT SRAM
内存宽度：	8	功能数量：	1
端子数量：	48	字数：	1024 words
字数代码：	1000	工作模式：	ASYNCHRONOUS
最高工作温度：	125 °C	最低工作温度：	-40 °C
组织：	1KX8	封装主体材料：	CERAMIC, GLASS-SEALED
封装形状：	RECTANGULAR	封装形式：	IN-LINE
并行/串行：	PARALLEL	认证状态：	Not Qualified
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	NO
技术：	CMOS	温度等级：	AUTOMOTIVE
端子形式：	THROUGH-HOLE	端子位置：	DUAL
Base Number Matches：	1

A1K-L67140V-55 数据手册

L67130/L67140

1 K × 8 CMOS Dual Port RAM 3.3 Volt

Introduction

The L67130/67140 are very low power CMOS dual port Using an array of eight transistors (8T) memory cell and

static RAMs organized as 1024 × 8. They are designed to fabricated with the state of the art 1.0 µm lithography

be used as a stand-alone 8 bits dual port RAM or as a named SCMOS, the M67130/140 combine an extremely

combination MASTER/SLAVE dual port for 16 bits or low standby supply current (typ = 1.0 µA) with a fast

more width systems. The MHS MASTER/SLAVE dual access time at 45 ns over the full temperature range. All

port approach in memory system applications results in versions offer battery backup data retention capability

full speed, error free operation without the need for with a typical power consumption at less than 5 µW.

additional discrete logic.

For military/space applications that demand superior

Master and slave devices provide two independent ports

with separate control, address and I/O pins that permit

independent, asynchronous access for reads and writes to

any location in the memory. An automatic power down

feature controlled by CS permits the onchip circuitry of

each port in order to enter a very low stand by power

mode.

levels of performance and reliability the L67130/67140

is processed according to the methods of the latest

revision of the MIL STD 883 (class B or S) and/or ESA

SCC 9000.

Features

D Single 3.3 V ± 0.3 volt power supply

D Fast access time

D On chip arbitration logic

D BUSY output flag on master

45 ns(*) to 70 ns

D BUSY input flag on slave

D 67130L/67140L low power

D INT flag for port to port communication

D Fully asynchronous operation from either port

D Battery backup operation : 2 V data retention

67130V/67140V very low power

D Expandable data bus to 16 bits or more using master/slave

devices when using more than one device.

(*) Preliminary

MATRA MHS

Rev. D (19 Fev. 97)

12 3 4 5 6 7...16

中文翻译

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与A1K-L67140V-55相关器件

型号	品牌	获取价格	描述	数据表
A1K-L67140V-70	TEMIC	获取价格	Dual-Port SRAM, 1KX8, 70ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48
A1K-L67142L-45	TEMIC	获取价格	Dual-Port SRAM, 2KX8, 45ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48
A1K-L67142L-55	ATMEL	获取价格	Dual-Port SRAM, 2KX8, 55ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48
A1K-L67142L-70	TEMIC	获取价格	Dual-Port SRAM, 2KX8, 70ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48
A1K-L67142V-45	TEMIC	获取价格	Dual-Port SRAM, 2KX8, 45ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48
A1K-L67142V-55	ATMEL	获取价格	Dual-Port SRAM, 2KX8, 55ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48
A1K-L67142V-70	TEMIC	获取价格	Dual-Port SRAM, 2KX8, 70ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48
A1KSMBJ10(C)A	GOOD-ARK	获取价格	TVS
A1KSMBJ11(C)A	GOOD-ARK	获取价格	TVS
A1KSMBJ12(C)A	GOOD-ARK	获取价格	TVS

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