L67130/L67140
Pin Names
LEFT PORT
RIGHT PORT
NAMES
CS
L
CS
R
Chip select
R/W
R/W
Write Enable
Output Enable
Address
L
R
OE
OE
R
L
A
A
0R – 9R
0L – 9L
I/O
I/O
Data Input/Output
Busy Flag
0L – 7L
0R – 7R
BUSY
BUSY
R
L
INT
INT
Interrupt Flag
Power
L
R
VCC
GND
Ground
Functional Description
The L 67130/L 67140 has two ports with separate control,
address and I/0 pins that permit independent read/write
access to any memory location. These devices have an
automatic power-down feature controlled by CS. CS
controls on-chip power-down circuitry which causes the
port concerned to go into stand-by mode when not
selected (CS high). When a port is selected access to the
full memory array is permitted. Each port has its own
Output Enable control (OE). In read mode, the port’s OE
turns the Output drivers on when set LOW.
Arbitration Logic
The arbitration logic will resolve an address match or a
chip select match down to a minimum of 5 ns and
determine which port has access. In all cases, an active
BUSY flag will be set for the inhibited port.
The BUSY flags are required when both ports attempt to
access the same location simultaneously.Should this
conflict arise, on-chip arbitration logic will determine
which port has access and set the BUSY flag for the
inhibited port. BUSY is set at speeds that allow the
processor to hold the operation with its associated address
and data. It should be noted that the operation is invalid
for the port for which BUSY is set LOW. The inhibited
port will be given access when BUSY goes inactive.
Non-conflicting
READ/WRITE
conditions
are
illustrated in table 1.
Interrupt Logic
The interrupt flag (INT) allows communication between
ports or systems. If the user chooses to use the interrupt
function, a memory location (mail box or message center)
A conflict will occur when both left and right ports are
active and the two addresses coincide. The on-chip
arbitration determines access in these circumstances.
Two modes of arbitration are provided : (1) if the
addresses match and are valid before CS on-chip control
is assigned to each port. The left port interrupt flag (INT )
L
is set when the right port writes to memory location 3FE
(HEX). The left port clears the interrupt by reading
address location 3FE. Similarly, the right port interrupt
logic arbitrates between CS and CS for access ; or (2)
L
R
if the CSs are low before an address match, on-chip
control logic arbitrates between the left and right
addresses for access (refer to table 2). The inhibited port’s
BUSY flag is set and will reset when the port granted
access completes its operation in both arbitration modes.
flag (INT ) is set when the left port writes to memory
R
location 3FF (hex), and the right port must read memory
location 3FF in order to clear the interrupt flag (INT ).
R
The 8 bit message at 3FE or 3FF is user-defined. If the
interrupt function is not used, address locations 3FE and
3FF are not reserved for mail boxes but become part of the
RAM. See table 3 for the interrupt function.
MATRA MHS
3
Rev. D (19 Fev. 97)
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