Datasheet > 9ZXL0852EKILF

9ZXL0852EKILF

更新时间： 2022-02-26 10:34:30

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
18页	274K
描述
8-Output DB800ZL Derivative PCIe Gen1â4 and UPI

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9ZXL0852EKILF 数据手册

9ZXL0832E / 9ZXL0852E Datasheet

Electrical Characteristics–Current Consumption

T_AMB= over the specified operating range. Supply voltages per normal operation conditions; see Test Loads for loading conditions

Symbol

Parameter

Conditions

Minimum

Typical Maximum Units

Notes

I_DDA

Operating Supply Current

V_DDA, PLL Mode at 100MHz

I_DD

Operating Supply Current

Powerdown Current

All other V_DDpins at 100MHz

V_DDA, CKPWRGD_PD# = 0

I_DDAPD

I_DDPD

All other V_DDpins, CKPWRGD_PD# = 0

^1.Includes VDDR if applicable.

Electrical Characteristics–HCSL/LP-HCSL Outputs

T_AMB= over the specified operating range. Supply voltages per normal operation conditions; see Test Loads for loading conditions

Specification

Limit

Symbol

Parameter

Conditions

Minimum Typical Maximum

Units Notes

dV/dt

ΔdV/dt

Vmax

Vmin

Vcross_abs

Δ-Vcross

Slew Rate

Slew Rate Matching

Max Voltage

Min Voltage

Crossing Voltage (abs)

Crossing Voltage (var)

Scope averaging on.

Single-ended measurement.

Measurement on single-ended signal using

absolute value (scope averaging off).

Scope averaging off.

2.9

7.1

792

-35

372

850

150

550

140

V/ns

1, 2, 3

1, 4, 7

–

660

-150

250

1150

-300

250 – 550

140

1, 5, 7

1, 6, 7

Scope averaging off.

¹Guaranteed by design and characterization, not 100% tested in production.

²Measured from differential waveform.

³Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V.

⁴Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point

where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations.

⁵Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and

Clock# falling).

⁶The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is to

limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.

⁷At default SMBus settings.

August 14, 2018

1...4 5 678 9 10...18

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与9ZXL0852EKILF相关器件

型号	品牌	获取价格	描述	数据表
9ZXL0852EKILFT	IDT	获取价格	8-Output DB800ZL Derivative PCIe Gen1â4 and
9ZXL0853E	RENESAS	获取价格	8-Output DB800ZL PCIe Zero-Delay/Fanout Clock Buffer with SMBus Write Protection
9ZXL1231	IDT	获取价格	12-output DB1200ZL
9ZXL1231	RENESAS	获取价格	DB1200ZL 12-Output Low Power HCSL Buffer
9ZXL1231_16	IDT	获取价格	12-output DB1200ZL
9ZXL1231AKILF	IDT	获取价格	12-output DB1200ZL
9ZXL1231AKILFT	IDT	获取价格	12-output DB1200ZL
9ZXL1231AKLF	IDT	获取价格	12-output DB1200ZL
9ZXL1231AKLFT	IDT	获取价格	12-output DB1200ZL
9ZXL1231E	IDT	获取价格	12-Output DB1200ZL for PCIe Gen1â4 and UPI

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