9ZXL0831
8-OUTPUT DB800ZL
Pin Descriptions
PIN #
PIN NAME
TYPE
DESCRIPTION
3.3V Input notifies device to sample latched inputs and start up on first high
1
CKPWRGD_PD#
IN assertion, or exit Power Down Mode on subsequent assertions. Low enters
Power Down Mode.
GND Ground pin.
2
3
GND
3.3V power for differential input clock (receiver). This VDD should be
VDDR
PWR
treated as an analog power rail and filtered appropriately.
4
5
6
7
DIF_IN
IN 0.7 V Differential True input
DIF_IN#
SMBDAT
SMBCLK
IN 0.7 V Differential Complementary Input
I/O Data pin of SMBUS circuitry, 5V tolerant
IN Clock pin of SMBUS circuitry, 5V tolerant
Complementary half of differential feedback output, provides feedback
signal to the PLL for synchronization with input clock to eliminate phase
error. This pin should NOT be connected on the circuit board, the feedback
is internal to the package.
True half of differential feedback output, provides feedback signal to the
PLL for synchronization with the input clock to eliminate phase error. This
pin should NOT be connected on the circuit board, the feedback is internal
8
9
DFB_OUT_NC#
DFB_OUT_NC
OUT
OUT
to the package.
10 VDD
PWR Power supply, nominal 3.3V
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
11 vOE0#
IN
12 NC
N/A No Connection.
13 DIF_0
14 DIF_0#
15 VDD
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
PWR Power supply, nominal 3.3V
16 DIF_1
17 DIF_1#
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
18 vOE1#
IN
19 VDD
20 NC
PWR Power supply, nominal 3.3V
N/A No Connection.
21 DIF_2
22 DIF_2#
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
23 vOE2#
24 vOE3#
IN
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
IN
25 DIF_3
26 DIF_3#
27 VDD
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
PWR Power supply, nominal 3.3V
28 DIF_4
29 DIF_4#
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
30 vOE4#
31 vOE5#
IN
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
IN
IDT® 8-OUTPUT DB800ZL
3
9ZXL0831
REV E 081616
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