Datasheet > 9ZXL0831AKLF

9ZXL0831AKLF

更新时间： 2022-02-26 11:26:50

品牌	Logo	应用领域
艾迪悌 - IDT		输出元件
页数	文件大小	规格书
18页	347K
描述
8-OUTPUT

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数据手册

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9ZXL0831AKLF 数据手册

9ZXL0831

8-OUTPUT DB800ZL

Pin Configuration

48 47 46 45 44 43 42 41 40 39 38 37

CKPWRGD_PD#

GND

DIF_6#

DIF_6

VDD

VDDR

DIF_IN

DIF_5#

DIF_5

vOE5#

vOE4#

DIF_4#

DIF_4

VDD

DIF_IN#

9ZXL0831

SMBDAT

SMBCLK

DFB_OUT_NC#

DFB_OUT_NC

VDD

Paddle is

pin 49

Connect to GND

vOE0#

DIF_3#

DIF_3

13 14 15 16 17 18 19 20 21 22 23 24

48-pin VFQFPN, 6x6 mm, 0.4mm pitch

Power Management Table

PLL STATE

IF NOT IN

DIF_IN/

DIF_IN#

SMBus

EN bit

DIF(7:0)/

DIF(7:0)#

Low/Low

Running

BYPASS

MODE

OFF

CKPWRGD_PD#

Running

Functionality at Power-up (PLL mode)

PLL Operating Mode Readback Table

DIF_IN

MHz

100.00

133.33

HiBW_BypM_LoBW#

Low (Low BW)

Byte0, bit 7

Byte 0, bit 6

100M_133M#

DIF(7:0)

DIF_IN

Mid (Bypass)

High (High BW)

Power Connections

Tri-Level Input Thresholds

Pin Number

Level

Low

Mid

Voltage

<0.8V

1.2<Vin<1.8V

Vin > 2.2V

Description

VDD

GND

Analog PLL

Analog Input

High

10,15,19,

27,34,38, 42

DIF clocks

PLL Operating Mode

HiBW_BypM_LoBW#

MODE

SMBus Address

Low

PLL Lo BW

Address

Read/Write bit

Mid

Bypass

1101100

High

PLL Hi BW

NOTE: PLL is OFF in Bypass Mode

IDT® 8-OUTPUT DB800ZL

9ZXL0831

REV E 081616

123 4 5 6 7...18

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