Datasheet > 9ZXL0632EKILF

9ZXL0632EKILF

更新时间： 2022-02-26 10:53:48

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
20页	302K
描述
6-Output DB800ZL Derivat ive for PCIe Gen1â4 and UPI

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9ZXL0632EKILF 数据手册

9ZXL0632E / 9ZXL0652E Datasheet

Table 1. Pin Descriptions (Cont.)

Number

Name

Type

Description

DIF0#

VDD

Output Differential complementary clock output.

Power Power supply, nominally 3.3V.

DIF1

Output Differential true clock output.

DIF1#

Output Differential complementary clock output.

Active low input for enabling output 1. This pin has an internal 120kΩ pull-down.

vOE1#

Input

1 = disable outputs, 0 = enable outputs.

VDD

Power Power supply, nominally 3.3V.

Active low input for enabling output 2. This pin has an internal 120kΩ pull-down.

1 = disable outputs, 0 = enable outputs.

vOE2#

Input

DIF2

DIF2#

VDD

Output Differential true clock output.

Output Differential complementary clock output.

Power Power supply, nominally 3.3V.

Output Differential true clock output.

DIF3

DIF3#

Output Differential complementary clock output.

Active low input for enabling output 3. This pin has an internal 120kΩ pull-down.

vOE3#

Input

1 = disable outputs, 0 = enable outputs.

VDD

Power Power supply, nominally 3.3V.

—

No connection.

Power Power supply, nominally 3.3V.

Active low input for enabling output 4. This pin has an internal 120kΩ pull-down.

1 = disable outputs, 0 = enable outputs.

VDD

vOE4#

Input

DIF4

DIF4#

VDD

Output Differential true clock output.

Output Differential complementary clock output.

Power Power supply, nominally 3.3V.

Output Differential true clock output.

DIF5

DIF5#

Output Differential complementary clock output.

Active low input for enabling output 5. This pin has an internal 120kΩ pull-down.

vOE5#

Input

1 = disable outputs, 0 = enable outputs.

VDD

VDDA

EPAD

Power Power supply, nominally 3.3V.

Power Power supply for PLL core.

GND

Ground pad.

August 14, 2018

1 2 3 456 7 8...20

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