Datasheet > 9ZXL0632EKILF

9ZXL0632EKILF

更新时间： 2022-02-26 10:53:48

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
20页	302K
描述
6-Output DB800ZL Derivat ive for PCIe Gen1â4 and UPI

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9ZXL0632EKILF 数据手册

9ZXL0632E / 9ZXL0652E Datasheet

PLL Operating Mode Readback Table

HiBW_BypM_LoBW#

Byte0, bit 7

Byte 0, bit 6

Low (Low BW)

Mid (Bypass)

High (High BW)

Pow er Connections

Pin Number

GND

Description

Analog PLL

Analog input

DIF clocks

12,16,20,21,25,29,31,35,39

Pin Descriptions

Table 1. Pin Descriptions

Number

Name

Type

Description

This pin prevents SMBus writes when asserted. SMBus reads are not affected. This pin has

an internal 120kΩ pull-down.

vSMB_WRTLOCK

Input

0 = SMBus writes allows, 1 = SMBus writes blocked.

Latched Tri-level input to select High BW, Bypass or Low BW Mode. Has an internal 120kΩ pull-up

^HIBW_BYPM_LOBW#

^CKPWRGD_PD#

resistor. See PLL Operating Mode table for details.

Input notifies device to sample latched inputs and start up on first high assertion. Low

enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin

has internal 120kΩ pull-up resistor.

Input

GND

Ground pin.

Power supply for differential input clock (receiver). This V should be treated as an analog

power rail and filtered appropriately. Nominally 3.3V.

VDDR

Power

DIF_IN

DIF_IN#

SMBDAT

SMBCLK

Input

I/O

HCSL true input.

HCSL complementary input.

Data pin of SMBUS circuitry.

Input

Clock pin of SMBUS circuitry.

Complementary half of differential feedback output. This pin should NOT be connected to

FBOUT_NC#

Output anything outside the chip. It exists to provide delay path matching to get 0 propagation

delay.

True half of differential feedback output. This pin should NOT be connected to anything

Output

FBOUT_NC

VDD

outside the chip. It exists to provide delay path matching to get 0 propagation delay.

Power Power supply, nominally 3.3V.

Active low input for enabling output 0. This pin has an internal 120kΩ pull-down.

vOE0#

DIF0

Input

1 = disable outputs, 0 = enable outputs.

Output Differential true clock output.

August 14, 2018

1 2 345 6 7...20

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