Datasheet > 9ZXL0632EKILF

9ZXL0632EKILF

更新时间： 2022-02-26 10:53:48

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
20页	302K
描述
6-Output DB800ZL Derivat ive for PCIe Gen1â4 and UPI

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9ZXL0632EKILF 数据手册

9ZXL0632E / 9ZXL0652E Datasheet

⁴Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a ±75mV window centered on the average

cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use

for the edge rate calculations.

⁵Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock

rising and Clock# falling).

⁶The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed.

The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.

⁷At default SMBus settings.

Table 9. Filtered Phase Jitter Parameters - PCIe Common Clocked (CC) Architectures

Industry

Limits

Parameter

Symbol

Conditions

Minimum Typical Maximum

Units Notes

PCIe Gen 1.

13.4

1,2,3

(p-p)

jphPCIeG1-CC

PCIe Gen 2 Low Band

10kHz < f < 1.5MHz

(PLL BW of 5–16MHz or 8–16MHz,

CDR = 5MHz).

1,2

0.2

0.7

(rms)

jphPCIeG2-CC

Phase Jitter,

PLL Mode

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

(PLL BW of 5–16MHz or 8–16MHz,

CDR = 5MHz).

1,2

1.0

1.5

3.1

(rms)

PCIe Gen 3 (PLL BW of 2–4MHz or

2–5MHz, CDR = 10MHz).

1,2

0.2

0.4

jphPCIeG3-CC

jphPCIeG4-CC

jphPCIeG1-CC

(rms)

PCIe Gen 4 (PLL BW of 2–4MHz or

2–5MHz, CDR = 10MHz).

1,2

0.5

(rms)

PCIe Gen 1.

0.01

0.06

1,2,3,4

(p-p)

PCIe Gen 2 Low Band

10kHz < f < 1.5MHz

(PLL BW of 5–16MHz or 8–16MHz,

CDR = 5MHz).

0.01

0.06

1,2,3,4

(rms)

jphPCIeG2-CC

Additive

PCIe Gen 2 High Band

Not

Applicable

Phase Jitter,

Bypass Mode

1.5MHz < f < Nyquist (50MHz)

(PLL BW of 5–16MHz or 8–16MHz,

CDR = 5MHz).

1,2,3,4

(rms)

PCIe Gen 3 (PLL BW of 2–4MHz or

2–5MHz, CDR = 10MHz).

0.01

0.06

1,2,3,4

(rms)

jphPCIeG3-CC

jphPCIeG4-CC

PCIe Gen 4 (PLL BW of 2–4MHz or

2–5MHz, CDR = 10MHz).

1,2,3,4

(rms)

August 14, 2018

1...7 8 91011 12 13...20

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与9ZXL0632EKILF相关器件

型号	品牌	获取价格	描述	数据表
9ZXL0632EKILFT	IDT	获取价格	6-Output DB800ZL Derivat ive for PCIe Gen1â
9ZXL0651	RENESAS	获取价格	6-Output Low-power Buffer for PCIe Gen1-2-3 and QPI with Zo=85 Ohms
9ZXL0651E	IDT	获取价格	6-Output DB800ZL Derivative for PCIe Gen1â4
9ZXL0651E	RENESAS	获取价格	6-Output DB800ZL PCIe Zero-Delay/Fanout Clock Buffer
9ZXL0651EKILF	IDT	获取价格	6-Output DB800ZL Derivative for PCIe Gen1â4
9ZXL0651EKILFT	IDT	获取价格	6-Output DB800ZL Derivative for PCIe Gen1â4
9ZXL0652E	IDT	获取价格	6-Output DB800ZL Derivat ive for PCIe Gen1â
9ZXL0652E	RENESAS	获取价格	6-Output DB800ZL PCIe Zero-Delay/Fanout Clock Buffer with SMBus Write Protection
9ZXL0652EKILF	IDT	获取价格	6-Output DB800ZL Derivat ive for PCIe Gen1â
9ZXL0652EKILFT	IDT	获取价格	6-Output DB800ZL Derivat ive for PCIe Gen1â

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