Datasheet > 9ZXL0631EKILFT

9ZXL0631EKILFT

更新时间： 2022-02-26 10:53:48

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
20页	303K
描述
6-Output DB800ZL Derivative for PCIe Gen1â4 and UPI

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9ZXL0631EKILFT 数据手册

9ZXL0631E / 9ZXL0651E Datasheet

Table 8. HCSL/LP-HCSL Outputs

Industry

Limits

Parameter

Symbol

Conditions

Minimum

Typical

Maximum

Units Notes

Slew Rate

dV/dt

Scope averaging on.

2.9

1 – 4

V/ns

1,2,3

1,4,7

Slew Rate

Matching

Single-ended measurement.

ΔdV/dt

Vmax

7.1

792

-35

372

1150

Maximum

Voltage

Measurement on single-ended

signal using absolute value (scope

averaging off).

660

-150

250

850

150

550

140

Minimum

Voltage

Vmin

-300

Crossing

Voltage (abs)

Scope averaging off.

Vcross_abs

Δ-Vcross

250 – 550

140

1,5,7

1,6,7

Crossing

Voltage (var)

¹Guaranteed by design and characterization, not 100% tested in production.

²Measured from differential waveform.

³Slew rate is measured through the Vswing voltage range centered around differential 0 V. This results in a ±150mV window around differential 0V.

⁴Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a ±75mV window centered on the average

cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use

for the edge rate calculations.

⁵Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock

rising and Clock# falling).

⁶The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed.

The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.

⁷At default SMBus settings.

Table 9. Filtered Phase Jitter Parameters - PCIe Common Clocked (CC) Architectures

Industry

Limits

Parameter

Symbol

Conditions

Minimum Typical Maximum

Units Notes

PCIe Gen 1.

13.4

1,2,3

(p-p)

jphPCIeG1-CC

PCIe Gen 2 Low Band

10kHz < f < 1.5MHz

(PLL BW of 5–16MHz or 8–16MHz,

CDR = 5MHz).

1,2

0.2

0.7

(rms)

jphPCIeG2-CC

Phase Jitter,

PLL Mode

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

(PLL BW of 5–16MHz or 8–16MHz,

CDR = 5MHz).

1,2

1.0

1.5

3.1

(rms)

PCIe Gen 3 (PLL BW of 2–4MHz or

2–5MHz, CDR = 10MHz).

1,2

0.2

0.4

jphPCIeG3-CC

jphPCIeG4-CC

(rms)

PCIe Gen 4 (PLL BW of 2–4MHz or

2–5MHz, CDR = 10MHz).

1,2

0.5

(rms)

August 14, 2018

1...6 7 8910 11 12...20

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