Datasheet > 9ZXL0631EKILFT

9ZXL0631EKILFT

更新时间： 2022-02-26 10:53:48

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
20页	303K
描述
6-Output DB800ZL Derivative for PCIe Gen1â4 and UPI

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9ZXL0631EKILFT 数据手册

9ZXL0631E / 9ZXL0651E Datasheet

Table 5. Input/Supply/Common Parameters (Cont.)

Parameter

Symbol

Conditions

Minimum

Typical

Maximum Units Notes

Input High Voltage

Input Mid Voltage

Input Low Voltage

Tri-level Inputs.

2.2

1.2

+ 0.3

1.8

GND - 0.3

-5

0.8

Single-ended inputs, V = GND, V = V

DD.

μA

Single-ended inputs.

Input Current

= 0 V; inputs with internal pull-up resistors.

-50

μA

INP

= V ; inputs with internal pull-down

resistors.

= 3.3V, Bypass Mode.

400

102.5

135

MHz

ibyp

Input Frequency

Pin Inductance

Capacitance

= 3.3V, 100MHz PLL Mode.

= 3.3V, 133.33MHz PLL Mode.

98.5

132

100.00

133.33

ipll

Logic inputs, except DIF_IN.

DIF_IN differential clock inputs.

Output pin capacitance.

1.5

INDIF_IN

2.7

1,4

OUT

From V power-up and after input clock

Clk Stabilization

stabilization or de-assertion of PD# to 1st

clock.

1.8

1,2

STAB

Input SS

Modulation

Frequency PCIe

Allowable frequency for PCIe applications

kHz

MODINPCIe (Triangular modulation).

DIF start after OE# assertion.

OE# Latency

clocks 1,2,3

LATOE#

DIF stop after OE# deassertion.

DIF output enable after PD# de-assertion.

Fall time of control inputs.

Tdrive_PD#

Tfall

300

μs

1,3

DRVPD

Trise

Rise time of control inputs.

¹Guaranteed by design and characterization, not 100% tested in production.

²Control input must be monotonic from 20% to 80% of input swing.

³Time from deassertion until outputs are > 200mV.

⁴DIF_IN input.

Table 6. Current Consumption

Parameter

Symbol

Conditions

Minimum Typical

Maximum Units Notes

Operating Supply Current

Power Down Current

, PLL Mode at 100MHz.

DDA

All other V pins at 100MHz.

, CKPWRGD_PD# = 0.

DDA

DDAPD

Power Down Current

All other V pins, CKPWRGD_PD# = 0.

DDPD

¹Includes V_DDRif applicable.

August 14, 2018

1...4 5 678 9 10...20

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