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9ZX21901DKLF PDF预览

9ZX21901DKLF

更新时间: 2024-02-07 22:34:53
品牌 Logo 应用领域
艾迪悌 - IDT PC驱动逻辑集成电路
页数 文件大小 规格书
20页 341K
描述
19-Output DB1900Z for PCIe Gen1-4 and QPI/UPI

9ZX21901DKLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:VFQFPN
包装说明:HVQCCN,针数:72
Reach Compliance Code:compliant风险等级:2.29
系列:9ZX输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-XQCC-N72JESD-609代码:e3
长度:10 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:72
实输出次数:38最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260座面最大高度:1 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10 mmBase Number Matches:1

9ZX21901DKLF 数据手册

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9ZX21901D DATASHEET  
Pin Configuration  
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55  
VDDA  
GNDA  
1
2
3
4
5
6
7
8
9
54 OE11#  
53 DIF_11#  
52 DIF_11  
51 OE10#  
50 DIF_10#  
49 DIF_10  
48 OE9#  
47 DIF_9#  
46 DIF_9  
45 VDD  
IREF  
100M_133M#  
HIBW_BYPM_LOBW#  
CKPWRGD_PD#  
GND  
9ZX21901D  
connect ePad to Ground  
NOTE: DFB_OUT pins must be  
terminated identically to the regular DIF  
outputs  
VDDR  
DIF_IN  
DIF_IN# 10  
SMB_A0_tri 11  
SMBDAT 12  
SMBCLK 13  
SMB_A1_tri 14  
NC 15  
44 GND  
43 OE8#  
42 DIF_8#  
41 DIF_8  
40 OE7#  
39 DIF_7#  
38 DIF_7  
37 OE6#  
NC 16  
DFB_OUT# 17  
DFB_OUT 18  
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36  
72-pin VFQFPN (10mm x10 mm, 0.5mm pad pitch)  
Power Connections  
Functionality at Power Up (PLL Mode)  
DIF_IN  
(MHz)  
100.00  
133.33  
DIF_x  
(MHz)  
Pin Number  
100M_133M#  
Description  
VDD  
GND  
1
0
DIF_IN  
DIF_IN  
1
8
2
7
Analog PLL  
Analog Input  
21, 31, 45,  
58, 68  
26, 44, 63  
DIF clocks  
PLL Operating Mode Readback Table  
HiBW_BypM_LoBW#  
Low (Low BW)  
Byte0, bit 7  
Byte 0, bit 6  
0
0
1
0
1
1
9ZX21901 SMBus Addressing  
Mid (Bypass)  
Pin  
SMBus Address  
(Rd/Wrt bit = 0)  
D8  
High (High BW)  
SMB_A1_tri SMB_A0_tri  
0
0
M
1
0
DA  
PLL Operating Mode  
HiBW_BypM_LoBW#  
Low  
0
DE  
C2  
C4  
MODE  
M
M
0
PLL Lo BW  
M
1
Mid  
Bypass  
M
1
C6  
CA  
CC  
CE  
High  
PLL Hi BW  
0
NOTE: PLL is OFF in Bypass Mode  
M
1
1
1
Tri-level Input Thresholds  
Level  
Low  
Voltage  
<0.8V  
Mid  
1.2<Vin<1.8V  
Vin > 2.2V  
High  
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI  
2
APRIL 17, 2018  

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