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9ZX21901DKLF PDF预览

9ZX21901DKLF

更新时间： 2024-02-13 00:55:08
品牌 Logo 应用领域
艾迪悌 - IDT PC驱动逻辑集成电路
页数 文件大小 规格书
20页 341K
描述
19-Output DB1900Z for PCIe Gen1-4 and QPI/UPI

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9ZX21901DKLF 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：VFQFPN
包装说明：HVQCCN,针数：72
Reach Compliance Code：compliant风险等级：2.29
系列：9ZX输入调节：DIFFERENTIAL MUX
JESD-30 代码：S-XQCC-N72JESD-609代码：e3
长度：10 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
湿度敏感等级：3功能数量：1
反相输出次数：端子数量：72
实输出次数：38最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260座面最大高度：1 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：10 mmBase Number Matches：1

9ZX21901DKLF 数据手册

 浏览型号9ZX21901DKLF的Datasheet PDF文件第14页浏览型号9ZX21901DKLF的Datasheet PDF文件第15页浏览型号9ZX21901DKLF的Datasheet PDF文件第16页浏览型号9ZX21901DKLF的Datasheet PDF文件第18页浏览型号9ZX21901DKLF的Datasheet PDF文件第19页浏览型号9ZX21901DKLF的Datasheet PDF文件第20页 
Revision History  
Issue Date Description  
1. Updated electrical tables  
9/16/2016  
2. Move to Final  
10/5/2016 Changed IDD maximum value from 450 to 490mA  
1. Features change: "Hardware or software control of PLL operating mode; change mode with software mode does not need  
power cycle."  
2. Change Max of Powerdown Current IDDPD to 5mA.  
3. Input frequency of PLL mode:  
(1). Change Min of 100MHz to 98.5HMz and Max of 100MHz to 102MHz.  
(2). Change Max of 133.33MHz to 130.5MHz and Max of 133.33MHz to 135MHz.  
4. DIF HCSL/LP-HCSL Outputs:  
(1). Change Min of Max Voltage to 719mV and Max of Max Voltage to 842mV.  
(2). Change Min of (Crossing Voltage (abs)) to 310mV and Max of (Crossing Voltage (abs)) to 400mV.  
5. Change Typ of Cycle to cycle jitter of PLL mode to 17ps.  
2/15/2017  
6.Filtered Phase Jitter Parameters - PCIe Common Clocked  
(CC) Architectures"  
(1).Change Typ of additive phase jitter of bypass mode of PCIe Gen1 to 0.1.  
(2). Change Typ and max of additive phase jitter of bypass mode of PCIe Gen2 Lo Band to 0.1.  
(3). Change Typ and max of additive phase jitter of bypass mode of PCIe Gen3 to 0.1.  
(4). Change Typ and max of additive phase jitter of bypass mode of PCIe Gen4 to 0.1.  
7.Unfiltered Phase Jitter Parameters - 12kHz to 20MHz  
(1). Change Min,TYP and Max of PLLmode High BW to 161, 178, 198ps.  
(2). Change Min,TYP and Max of PLLmode Low BW to 175, 193, 207ps.  
(3). Change Min,TYP and Max of Bpmode to 104, 104, 110ps.  
12/1/2017 Removed “5V tolerant” reference in pins 12 and 13 descriptions.  
4/17/2018 Updated absolute maximum supply voltage rating and VIHSMB to 3.9V.  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
Tech Support  
www.idt.com/go/support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without  
notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed  
in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any  
particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intel-  
lectual property rights of IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of  
IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.  
9ZX21901D APRIL 17, 2018  
17  
©2018 Integrated Device Technology, Inc.  
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