Datasheet > 9ZX21901D

9ZX21901D

更新时间： 2022-02-26 11:51:14

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
20页	341K
描述
19-Output DB1900Z for PCIe Gen1-4 and QPI/UPI

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数据手册

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9ZX21901D 数据手册

9ZX21901D DATASHEET

Pin Configuration

72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55

VDDA

GNDA

54 OE11#

53 DIF_11#

52 DIF_11

51 OE10#

50 DIF_10#

49 DIF_10

48 OE9#

47 DIF_9#

46 DIF_9

45 VDD

IREF

100M_133M#

HIBW_BYPM_LOBW#

CKPWRGD_PD#

GND

9ZX21901D

connect ePad to Ground

NOTE: DFB_OUT pins must be

terminated identically to the regular DIF

outputs

VDDR

DIF_IN

DIF_IN# 10

SMB_A0_tri 11

SMBDAT 12

SMBCLK 13

SMB_A1_tri 14

NC 15

44 GND

43 OE8#

42 DIF_8#

41 DIF_8

40 OE7#

39 DIF_7#

38 DIF_7

37 OE6#

NC 16

DFB_OUT# 17

DFB_OUT 18

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

72-pin VFQFPN (10mm x10 mm, 0.5mm pad pitch)

Power Connections

Functionality at Power Up (PLL Mode)

DIF_IN

(MHz)

100.00

133.33

DIF_x

(MHz)

Pin Number

100M_133M#

Description

VDD

GND

DIF_IN

Analog PLL

Analog Input

21, 31, 45,

58, 68

26, 44, 63

DIF clocks

PLL Operating Mode Readback Table

HiBW_BypM_LoBW#

Low (Low BW)

Byte0, bit 7

Byte 0, bit 6

9ZX21901 SMBus Addressing

Mid (Bypass)

SMBus Address

(Rd/Wrt bit = 0)

High (High BW)

SMB_A1_tri SMB_A0_tri

PLL Operating Mode

HiBW_BypM_LoBW#

Low

MODE

PLL Lo BW

Mid

Bypass

High

PLL Hi BW

NOTE: PLL is OFF in Bypass Mode

Tri-level Input Thresholds

Level

Low

Voltage

<0.8V

Mid

1.2<Vin<1.8V

Vin > 2.2V

High

19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI

APRIL 17, 2018

123 4 5 6 7...20

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