Datasheet > 9ZX21901D

9ZX21901D

更新时间： 2022-02-26 11:51:14

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
20页	341K
描述
19-Output DB1900Z for PCIe Gen1-4 and QPI/UPI

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9ZX21901D 数据手册

9ZX21901D DATASHEET

Electrical Characteristics – Current Consumption

Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS NOTES

Operating Supply Current

Powerdown Current

I_DDA

I_DD

VDDA, PLL Mode@100MHz

All other VDD pins

466

490

I_DDPD

All DIF pairs Hi-Z

Includes VDDR if applicable

Electrical Characteristics – Input/Supply/Common Parameters

Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions

PARAMETER

SYMBOL

VDDx

CONDITIONS

MIN

TYP

3.3

MAX

UNITS NOTES

Supply Voltage

Ambient Operating

Temperature

Supply voltage for core and analog

3.135

3.465

T_AMB

V_IH

Commercial range (T_COM

)

°C

Single-ended inputs, except SMBus, tri-level

Input High Voltage

V_DD+ 0.3

0.8

inputs

Single-ended inputs, except SMBus, tri-level

inputs

Input Low Voltage

V_IL

GND - 0.3

Input High Voltage

Input Mid Voltage

Input Low Voltage

V_IH

V_IL

I_IN

Tri-Level Inputs

2.2

1.2

V_DD+ 0.3

Tri-Level Inputs

VDD/2

1.8

0.8

GND - 0.3

-5

Single-ended inputs, V_IN= GND, V_IN= VDD

µA

Single-ended inputs

Input Current

V_IN= 0 V; Inputs with internal pull-up resistors

_IN= VDD; Inputs with internal pull-down resistors

I_INP

-200

200

µA

F_ibyp

F_ipll

V_DD= 3.3 V, Bypass mode

V_DD= 3.3 V, 100MHz PLL mode

V_DD= 3.3 V, 133.33MHz PLL mode

400

102

135

MHz

Input Frequency

Pin Inductance

Capacitance

98.5

125

100.00

130.50

F_ipll

L_pin

C_IN

Logic Inputs, except DIF_IN

DIF_IN differential clock inputs

Output pin capacitance

1.5

C_{INDIF_IN}

C_OUT

2.7

1,4

From V_DDPower-Up and after input clock

Clk Stabilization

T_STAB

1.4

1.8

1,2

stabilization or de-assertion of PD# to 1st clock

Input SS Modulation

Frequency PCIe

Allowable Frequency for PCIe Applications

(Triangular Modulation)

f_MODINPCIe

t_LATOE#

t_DRVPD

kHz

DIF start after OE# assertion

DIF stop after OE# deassertion

DIF output enable after

OE# Latency

Tdrive_PD#

clocks 1,2,3

300

µs

1,3

PD# de-assertion

Tfall

t_F

Fall time of control inputs

Rise time of control inputs

Trise

t_R

¹Guaranteed by design and characterization, not 100% tested in production.

²Control input must be monotonic from 20% to 80% of input swing.

³Time from deassertion until outputs are > 200 mV.

⁴DIF_IN input.

19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI

APRIL 17, 2018

1...3 4 567 8 9...20

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