Datasheet > 9DBL0243

9DBL0243

更新时间： 2023-12-20 18:44:28

品牌	Logo	应用领域
瑞萨 - RENESAS		PC
页数	文件大小	规格书
32页	1355K
描述
2-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer with Loss of Signal Indicator

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数据手册

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9DBL0243 数据手册

Package Outline Drawing

Package Code: NDG48P1

48-VFQFPN 6.0 x 6.0 x 0.9 mm Body, 0.4 mm Pitch

PSC-4212-01, Revision: 02, Date Created: Nov 18, 2022

6.00 ±0.10

0.40

(0.55)

Pin 1 ID

0.20

6.00 ±0.10

4.10 ±0.10

0.20

4.10 ±0.10

0.40

BOTTOM VIEW

TOP VIEW

0.90 ±0.10

0.05 Max

0.08 C

Seating Plane

(0.20)

SIDE VIEW

6.30

5.20

Package

Outline

0.20

0.40

0.20

4.10

6.30

5.20

0.40

NOTES:

1. JEDEC compatible.

2. All dimensions are in mm and angles are in degrees.

3. Use ±0.50 mm for the non-toleranced dimensions.

4. Numbers in ( ) are for references only.

0.55

4.10

RECOMMENDED LAND PATTERN

(PCB Top View, NSMD Design)

1...28 29 303132

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与9DBL0243相关器件

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9DBL0243ANLGI	IDT	2-Output 3.3V LP-HCSL Zero-Delay Buffer with LOS Indicator	获取价格
9DBL0243ANLGI8	IDT	2-Output 3.3V LP-HCSL Zero-Delay Buffer with LOS Indicator	获取价格
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9DBL0252	RENESAS	2-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer	获取价格
9DBL0252BKILF	IDT	2-output 3.3V PCIe Zero-Delay Buffer	获取价格
9DBL0252BKILFT	IDT	2-output 3.3V PCIe Zero-Delay Buffer	获取价格
9DBL0253	RENESAS	2-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer with Loss of Signal Indicator	获取价格
9DBL0253ANLGI	IDT	2-Output 3.3V LP-HCSL Zero-Delay Buffer with LOS Indicator	获取价格
9DBL0253ANLGI8	IDT	2-Output 3.3V LP-HCSL Zero-Delay Buffer with LOS Indicator	获取价格
9DBL0255	RENESAS	2-Output 3.3V PCIe Gen1–5 Clock Fanout Buffer	获取价格