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9DBL0243 PDF预览

9DBL0243

更新时间: 2023-12-20 18:44:28
品牌 Logo 应用领域
瑞萨 - RENESAS PC
页数 文件大小 规格书
32页 1355K
描述
2-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer with Loss of Signal Indicator

9DBL0243 数据手册

 浏览型号9DBL0243的Datasheet PDF文件第24页浏览型号9DBL0243的Datasheet PDF文件第25页浏览型号9DBL0243的Datasheet PDF文件第26页浏览型号9DBL0243的Datasheet PDF文件第28页浏览型号9DBL0243的Datasheet PDF文件第29页浏览型号9DBL0243的Datasheet PDF文件第30页 
9DBL02x3/9DBL04x3/ 9DBL06x3/9DBL08x3 Datasheet  
Revision History  
Table 40. Revision History  
Revision Date  
Description of Change  
December 9, 2022  
January 24, 2021  
Added package links to Ordering Information; no technical changes were made.  
Added missing cross reference to Table 17 (ZDB Operating Mode) into Table 22 (Byte 1 description).  
Added minor updates to Table 17 for clarity and consistency.  
Changed the shipping package for the 9DBL0243A and 0253A from “Cut Tape” to “Trays” in the Ordering  
Information table.  
August 13, 2020  
Merged 9DBL02x2, 9DBL04x2, 9DBL06x1 and 9DBL08x1 into single document.  
Updated PCIe jitter tables to show PCIe Gen5.  
July 22, 2020  
Updated Test Loads figures to indicate PCIe Jitter Test setup.  
Updated package outline drawings link for the 9DBL08x3 devices to NDG48P1.  
Updated ordering information.  
March 15, 2020  
February 1, 2017  
February 1, 2017  
February 1, 2017  
Last update of 9DBL0243/253 Datasheet.  
Last update of 9DBL0443/0453 Datasheet.  
Last update of 9DBL0643/0653 Datasheet.  
Last update of 9DBL0843/0853 Datasheet.  
©2020 Renesas Electronics Corporation  
27  
December 9, 2022  

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