Datasheet > 9DBL0243

9DBL0243

更新时间： 2023-12-20 18:44:28

品牌	Logo	应用领域
瑞萨 - RENESAS		PC
页数	文件大小	规格书
32页	1355K
描述
2-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer with Loss of Signal Indicator

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数据手册

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9DBL0243 数据手册

Package Outline Drawing

Package Code:NLG32P1

32-VFQFPN 5.0 x 5.0 x 0.9 mm Body, 0.5mm Pitch

PSC-4171-01, Revision: 04, Date Created: Aug 15, 2022

(0.525)

0.50

5.00 ±0.10

Pin 1 ID

0.20

5.00 ±0.10

0.25

3.15 ±0.15

0.40

3.15 ±0.15

BOTTOM VIEW

TOP VIEW

0.90 ±0.10

0.08 C

Seating Plane

(0.20)

0.05 Max

SIDE VIEW

5.30

Package

Outline

0.25

0.50

0.20

3.15

4.20 5.30

NOTES:

1. JEDEC compatible.

2. All dimensions are in mm and angles are in degrees.

3. Use ±0.05 mm for the non-toleranced dimensions.

4. Numbers in ( ) are for references only.

3.15

RECOMMENDED LAND PATTERN

(PCB Top View, NSMD Design)

1...26 27 282930 31 32

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