Datasheet > 9DBL02

9DBL02

更新时间： 2022-02-26 11:00:07

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
19页	300K
描述
2-output 3.3V PCIe Zero-Delay Buffer

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数据手册

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9DBL02 数据手册

9DBL02 DATASHEET

SMBus Table: Pull-up Pull-down Control

Byte 15

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Control Function

Reserved

Type

Default

Reserved

OE1_pu/pd[1]

OE1_pu/pd[0]

OE1 Pull-up(PuP)/

Pull-down(Pdwn) control

00=None

01=Pdwn

10=Pup

11 = Pup+Pdwn

Note: These values are for xx42, and xx52. P2 is factory programmable.

SMBus Table: Pull-up Pull-down Control

Byte 16

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Control Function

Reserved

Type

Default

Reserved

CKPWRGD_PD_pu/pd[1]

CKPWRGD_PD_pu/pd[0]

CKPWRGD_PD Pull-up(PuP)/ RW

00=None

01=Pdwn

10=Pup

11 = Pup+Pdwn

Pull-down(Pdwn) control

Note: xx42 = 10, xx52 = 01, P2 = factory programmable.

Bytes 17 is Reserved

SMBus Table: Polarity Control

Byte 18

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Control Function

Reserved

Type

Default

Reserved

Sets OE1 polarity

Sets OE0 polarity

Reserved

OE1_polarity

OE0_polarity

RW Enabled when Low Enabled when High

Reserved

SMBus Table: Polarity Control

Byte 19

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

Control Function

Type

Default

Reserved

Determines

CKPWRGD_PD polarity

Power Down when Power Down when

Low High

CKPWRGD_PD

Bit 0

2-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER

OCTOBER 6, 2016

1...11 12 131415 16 17...19

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