9DB233
Two Output Differential Buffer for PCIe Gen3
Datasheet
Electrical Characteristics - Absolute Maximum Ratings
PARAMETER
SYMBOL
CONDITIONS
UNITS NOTES
MIN
TYP
MAX
4.6
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Input Low Voltage
VDDA
VDD
VIL
V
V
V
V
1,2
1,2
1
4.6
GND-0.5
Input High Voltage
VIH
Except for SMBus interface
SMBus clock and data pins
VDD+0.5V
5.5V
1
Input High Voltage
VIHSMB
V
1
°C
°C
V
1
1
1
Storage Temperature
Junction Temperature
Input ESD protection
Ts
Tj
-65
150
125
ESD prot
Human Body Model
2000
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
Electrical Characteristics - Input/Supply/Common Parameters
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
TCOM
TIND
Commmercial range
0
70
85
°C
°C
1
1
Ambient Operating
Temperature
Industrial range
-40
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Input High Voltage
Input Low Voltage
VIH
2
VDD + 0.3
V
1
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
VIL
IIN
GND - 0.3
-5
0.8
5
V
1
1
Single-ended inputs, VIN = GND, VIN = VDD
uA
Single-ended inputs
Input Current
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
IINP
-200
200
uA
1
Fibyp
Fipll
VDD = 3.3 V, Bypass mode
10
33
110
110
7
MHz
MHz
nH
2
2
Input Frequency
Pin Inductance
VDD = 3.3 V, 100MHz PLL mode
100.00
Lpin
1
CIN
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
1.5
1.5
5
pF
1
CINDIF_IN
2.7
pF
1,4
Capacitance
COUT
Output pin capacitance
6
pF
1
From VDD Power-Up and after input clock
Clk Stabilization
TSTAB
1.8
ms
1,2
stabilization or de-assertion of PD# to 1st clock
Input SS Modulation
Frequency
Allowable Frequency
fMODIN
30
1
33
kHz
1
(Triangular Modulation)
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
OE# Latency
Tdrive_PD#
tLATOE#
tDRVPD
3
cycles
us
1,3
1,3
300
PD# de-assertion
Tfall
tF
Fall time of control inputs
5
5
ns
ns
V
1,2
1,2
1
Trise
tR
Rise time of control inputs
SMBus Input Low Voltage
SMBus Input High Voltage
VILSMB
VIHSMB
0.8
2.1
VDDSMB
0.4
V
1
SMBus Output Low Voltage VOLSMB
@ IPULLUP
@ VOL
V
1
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
IPULLUP
VDDSMB
tRSMB
4
mA
V
1
3V to 5V +/- 10%
2.7
5.5
1000
300
1
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
ns
ns
1
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tFSMB
1
fMAXSMB
Maximum SMBus operating frequency
100
kHz
1,5
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
4DIF_IN input
5The differential input clock must be running for the SMBus to be active
IDT® Two Output Differential Buffer for PCIe Gen3
1667C—04/20/11
4
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