9DB233AFLF

更新时间： 2024-01-07 20:50:32

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
14页	197K
描述
Two Output Differential Buffer for PCIe Gen3

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9DB233AFLF 数据手册

9DB233

Two Output Differential Buffer for PCIe Gen3

Datasheet

Electrical Characteristics - Output Duty Cycle, Jitter, Skew and PLL Characterisitics

TA = T_COMor T_IND;Supply Voltage VDD = 3.3 V +/-5%

PARAMETER

PLL Bandwidth

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

-3dB point in High BW Mode

-3dB point in Low BW Mode

Peak Pass band Gain

2.3

0.5

MHz

0.4

PLL Jitter Peaking

Duty Cycle

t_JPEAK

t_DC

Measured differentially, PLL Mode

-2

Duty Cycle Distortion

Skew, Input to Output

t_DCD

Measured differentially, Bypass Mode @100MHz

1,4

t_pdBYP

t_pdPLL

t_sk3

Bypass Mode, V_T= 50%

2500

-250

3660

4500

250

Hi BW PLL Mode V_T= 50%

Skew, Output to Output

Jitter, Cycle to cycle

V_T= 50%

PLL mode

1,3

t_jcyc-cyc

Additive Jitter in Bypass Mode

¹Guaranteed by design and characterization, not 100% tested in production.

Ω

I_REF= V_DD/(3xR_R). For R_R= 475 (1%), I_REF= 2.32mA. I_OH= 6 x I_REFand V_OH= 0.7V @ Z_O=50 .

³Measured from differential waveform

⁴Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.

Electrical Characteristics - PCIe Phase Jitter Parameters

TA = T_COMor T_IND;Supply Voltage VDD = 3.3 V +/-5%

PARAMETER

SYMBOL

t_jphPCIeG1

CONDITIONS

PCIe Gen 1

MIN

TYP

MAX

UNITS Notes

ps (p-p) 1,2,3

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

1,2

1.1

2.3

0.5

3.1

(rms)

t_jphPCIeG2

Phase Jitter, PLL Mode

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

PCIe Gen 3

1,2

(rms)

t_jphPCIeG3

t_jphPCIeG1

1,2,4

(rms)

(PLL BW of 2-4MHz, CDR = 10MHz)

PCIe Gen 1

0.3

ps (p-p) 1,2,3

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

1,2

0.2

0.8

0.1

Additive Phase Jitter,

Bypass Mode

(rms)

t_jphPCIeG2

PCIe Gen 2 High Band

1,2

1.5MHz < f < Nyquist (50MHz)

PCIe Gen 3

(rms)

1,2,4

(rms)

0.2

t_jphPCIeG3

(PLL BW of 2-4MHz, CDR = 10MHz)

¹Applies to all outputs.

²See http://www.pcisig.com for complete specs

³Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.

⁴Subject to final radification by PCI SIG.

IDT^®Two Output Differential Buffer for PCIe Gen3

1667C—04/20/11

1...3 4 567 8 9...14

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