PCI Express Jitter Attenuator
ICS9DB306
DATA SHEET
GENERAL DESCRIPTION
FEATURES
The ICS9DB306 is a high performance 1-to-6 Differential-to-
LVPECL Jitter Attenuator designed for use in PCI Express™
systems. In some PCI Express systems, such as those found in
desktop PCs, the PCI Express clocks are generated from a low
bandwidth, high phase noise PLL frequency synthesizer. In
these systems, a zero delay buffer may be required to attenuate
high frequency random and deterministic jitter components from
the PLL synthesizer and from the system board. The ICS9DB306
has 2 PLL bandwidth modes. In low bandwidth mode, the PLL
loop BW is about 500kHz and this setting will attenuate much of
the jitter from the reference clock input while being high enough
to pass a triangular input spread spectrum profile. There is also
a high bandwidth mode which sets the PLL bandwidth at 1MHz
which will pass more spread spectrum modulation.
• Six differential LVPECL output pairs
• One differential clock input
• CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum output frequency: 140MHz
• Input frequency range: 90MHz - 140MHz
• VCO range: 450MHz - 700MHz
• Output skew: 135ps (maximum)
• Cycle-to-Cycle jitter: 30ps (maximum)
• RMS phase jitter @ 100MHz, (1.5MHz - 22MHz): 3ps (typical)
• 3.3V operating supply
For serdes which have x30 reference multipliers instead of x25
multipliers, 5 of the 6 PCI Express outputs (PCIEX1:5) can be
set for 125MHz instead of 100MHz by configuring the appropriate
frequency select pins (FS0:1). Output PCIEX0 will always run at
the reference clock frequency (usually 100MHz) in desktop PC
PCI Express Applications.
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
1 Disabled
nOE0
0 Enabled
1
2
3
4
28
27
26
VEE
VCC
PCIEXC0
PCIEXT0
FS0
nCLK
CLK
PCIEXT1
PCIEXC1
0
PCIEXT0
nPCIEXC0
÷5
1
25
PCIEXT2
PCIEXC2
VCC
24
23
22
5
6
7
8
Buffer
PLL_BW
VCCA
nOE0
nOE1
21
20
19
18
17
16
15
CLK
Loop
Filter
PCIEXT1
nPCIEXC1
VEE
VCC
9
0
1
Phase
Detector
0 ÷4
1 ÷5
VCO
nCLK
BYPASS
FS1
PCIEXC3
PCIEXT3
PCIEXC4
PCIEXT4
VEE
10
11
12
13
PCIEXT2
nPCIEXC2
PCIEXT5
PCIEXC5
VCC
FS0
14
÷5
ICS9DB306
28-Lead TSSOP, 173-MIL
4.4mm x 9.7mm x 0.925mm
body package
Internal Feedback
PCIEXT3
nPCIEXC3
0
1
0 ÷5
1 ÷4
L Package
Top View
PCIEXT4
nPCIEXC4
PCIEXT5
nPCIEXC5
ICS9DB306
28-Lead, 209-MIL SSOP
5.3mm x 10.2mm x 1.75mm
body package
FS1
BYPASS
nOE1
F Package
Top View
1 Disabled
0 Enabled
ICS9DB306BL REVISION C MARCH 14, 2012
1
©2012 Integrated Device Technology, Inc.