Datasheet > 97U877AKT

97U877AKT

更新时间： 2024-11-11 07:29:35

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
13页	640K
描述
VFQFPN-40, Reel

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中文翻译

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数据手册

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97U877AKT 数据手册

ICS97U877

Integrated

Circuit

Systems,Inc.

1.8V Wide Range Frequency Clock Driver

RecommendedApplication:

Pin Configuration

•

DDR2 Memory Modules / Zero Delay Board Fan Out

Provides complete DDR DIMM logic solution with

ICSSSTU32864

ProductDescription/Features:

•

Low skew, low jitter PLL clock driver

1 to 10 differential clock distribution (SSTL_18)

Feedback pins for input to output synchronization

Spread Spectrum tolerant inputs

Auto PD when input signal is at a certain logic state

SwitchingCharacteristics:

52-Ball BGA

•

Period jitter:40ps

Half-period jitter: 60ps

CYCLE - CYCLE jitter 40ps

OUTPUT - OUTPUT skew: 40ps

Top View

CLKT1

CLKC1

CLKC2

CLKT2

CLK_INT

CLK_INC

AGND

AVDD

CLKT3

CLKC3

CLKT0

GND

VDDQ

GND

CLKC0

GND

CLKC5

GND

CLKT5

GND

CLKT6

CLKC6

CLKC7

CLKT7

VDDQ

GND

CLKC9

FB_INT

FB_INC

FB_OUTC

FB_OUTT

CLKT8

VDDQ

GND

CLKT4

GND

CLKT9

CLKC4

CLKC8

Block Diagram

CLKT0

CLKC0

LD* or OE

Powerdown

Control and

Test Logic

CLKT1

CLKC1

LD*, OS or OE

AV_DD

CLKT2

CLKC2

PLL bypass

LD*

CLKT3

CLKC3

VDDQ

CLKC7

CLKC2

CLKT2

CLK_INT

CLK_INC

VDDQ

AGND

AVDD

VDDQ

CLKT7

VDDQ

FB_INT

FB_INC

FB_OUTC

FB_OUTT

VDDQ

CLKT4

CLKC4

CLKT5

CLKC5

ICS97U877

CLK_INT

CLKT6

CLKC6

CLK_INC

10K-100k

CLKT7

CLKC7

GND ¹⁰

PLL

GND

CLKT8

CLKC8

FB_INT

FB_INC

CLKT9

CLKC9

* The Logic Detect (LD) powers down the device when a

logic low is applied to both CLK_INT and CLK_INC.

40-Pin MLF

FB_OUTT

FB_OUTC

0792A—04/15/04

12 3 4 5 6 7...13

中文翻译

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与97U877AKT相关器件

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97ULP877BH	IDT	获取价格	CABGA-52, Tray
97ULP877BHLF-T	IDT	获取价格	PLL Based Clock Driver, 97ULP Series, 10 True Output(s), 0 Inverted Output(s), PBGA52, LEA
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97ULP877BKLF-T	IDT	获取价格	PLL Based Clock Driver, 97ULP Series, 10 True Output(s), 0 Inverted Output(s), PQCC40, LEA