ICS97U877
Integrated
Circuit
Systems,Inc.
1.8V Wide Range Frequency Clock Driver
RecommendedApplication:
Pin Configuration
•
•
DDR2 Memory Modules / Zero Delay Board Fan Out
Provides complete DDR DIMM logic solution with
ICSSSTU32864
1
2
3
4
5
6
A
B
C
D
E
F
ProductDescription/Features:
•
•
•
•
•
Low skew, low jitter PLL clock driver
1 to 10 differential clock distribution (SSTL_18)
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
G
H
J
Auto PD when input signal is at a certain logic state
K
SwitchingCharacteristics:
52-Ball BGA
•
•
•
•
Period jitter:40ps
Half-period jitter: 60ps
CYCLE - CYCLE jitter 40ps
OUTPUT - OUTPUT skew: 40ps
Top View
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
CLKT1
CLKC1
CLKC2
CLKT2
CLK_INT
CLK_INC
AGND
AVDD
CLKT3
CLKC3
CLKT0
GND
GND
VDDQ
VDDQ
VDDQ
VDDQ
GND
CLKC0
GND
NB
CLKC5
GND
NB
CLKT5
GND
GND
OS
CLKT6
CLKC6
CLKC7
CLKT7
VDDQ
NB
VDDQ
NB
VDDQ
OE
VDDQ
GND
GND
CLKC9
FB_INT
FB_INC
FB_OUTC
FB_OUTT
CLKT8
NB
NB
VDDQ
NB
VDDQ
NB
GND
GND
CLKT4
GND
CLKT9
K
CLKC4
CLKC8
Block Diagram
CLKT0
CLKC0
LD* or OE
OE
Powerdown
Control and
Test Logic
CLKT1
CLKC1
LD*, OS or OE
OS
AVDD
CLKT2
CLKC2
40
31
PLL bypass
LD*
CLKT3
CLKC3
30
1
VDDQ
CLKC7
CLKC2
CLKT2
CLK_INT
CLK_INC
VDDQ
AGND
AVDD
VDDQ
CLKT7
VDDQ
FB_INT
FB_INC
FB_OUTC
FB_OUTT
VDDQ
OE
CLKT4
CLKC4
CLKT5
CLKC5
ICS97U877
CLK_INT
CLKT6
CLKC6
CLK_INC
10K-100k
CLKT7
CLKC7
GND 10
21
PLL
OS
GND
11
20
CLKT8
CLKC8
FB_INT
FB_INC
CLKT9
CLKC9
* The Logic Detect (LD) powers down the device when a
logic low is applied to both CLK_INT and CLK_INC.
40-Pin MLF
FB_OUTT
FB_OUTC
0792A—04/15/04