Datasheet > 97U877KLF-T

97U877KLF-T

更新时间： 2024-01-08 12:29:27

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
13页	129K
描述
Clock Driver

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技术参数
数据手册

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97U877KLF-T 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	,	Reach Compliance Code：	compliant
风险等级：	5.84	Base Number Matches：	1

97U877KLF-T 数据手册

ICS97U877

Timing Requirements

T_A= 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)

CONDITIONS

MIN

MAX

370

PARAMETER

SYMBOL

freq_op

UNITS

MHz

Max clock frequency

1.8V+0.1V @ 25°C

freq_App

d_tin

Application Frequency Range

Input clock duty cycle

CLK stabilization

1.8V+0.1V @ 25°C

160

350

MHz

T_STAB

µs

Switching Characteristics¹

T_A= 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)

PARAMETER

Output enable time

Output disable time

Period jitter

SYMBOL

t_en

CONDITION

OE to any output

MIN

TYP

4.73

5.82

MAX UNITS

t_dis

OE to any output

t_{jit (per)}

t_jit(hper)

-30

-60

0.5

1.5

Half-period jitter

Input Clock

Output Enable (OE), (OS)

2.5

v/ns

Input slew rate

SLr1(i)

Output clock slew rate

Cycle-to-cycle period jitter

SLr1(o)

t_jit(cc+)

-40

t_jit(cc-)

t_{( )dyn}

Dynamic Phase Offset

Static Phase Offset

-20

-50

t_SPO

t_skew

Output to Output Skew

SSC modulation frequency

SSC clock input frequency

deviation

kHz

30.00

0.00

-0.50

PLL Loop bandwidth (-3 dB

from unity gain)

2.0

MHz

Notes:

1. Switching characteristics guaranteed for application frequency range.

2. Static phase offset shifted by design.

0792A—04/15/04

1...3 4 567 8 9...13

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