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97ULP877BH-T PDF预览

97ULP877BH-T

更新时间: 2024-02-21 07:21:16
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
15页 252K
描述
PLL Based Clock Driver, 97ULP Series, 10 True Output(s), 0 Inverted Output(s), PBGA52, MO-205, MO-225, BGA-52

97ULP877BH-T 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:BGA包装说明:VFBGA, BGA52,6X10,25
针数:52Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.22
Is Samacsys:N系列:97ULP
输入调节:DIFFERENTIALJESD-30 代码:R-PBGA-B52
JESD-609代码:e0长度:7 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:52实输出次数:10
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:VFBGA封装等效代码:BGA52,6X10,25
封装形状:RECTANGULAR封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:1.8 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.04 ns
座面最大高度:1 mm子类别:Clock Drivers
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn63Pb37)
端子形式:BALL端子节距:0.65 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.5 mm最小 fmax:410 MHz
Base Number Matches:1

97ULP877BH-T 数据手册

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ICS97ULP877B  
Integrated  
Circuit  
Systems,Inc.  
1.8V Low-Power Wide-Range Frequency Clock Driver  
RecommendedApplication:  
Pin Configuration  
DDR2 Memory Modules / Zero Delay Board Fan Out  
Provides complete DDR DIMM logic solution with  
ICSSSTU32864/SSTUF32864/SSTUF32866  
1
2
3
4
5
6
A
B
C
D
E
F
ProductDescription/Features:  
Low skew, low jitter PLL clock driver  
1 to 10 differential clock distribution (SSTL_18)  
Feedback pins for input to output synchronization  
Spread Spectrum tolerant inputs  
G
H
J
Auto PD when input signal is at a certain logic state  
K
SwitchingCharacteristics:  
52-Ball BGA  
Period jitter:40ps  
Half-period jitter: 60ps  
CYCLE - CYCLE jitter 40ps  
OUTPUT - OUTPUT skew: 40ps  
Top View  
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
CLKT1  
CLKC1  
CLKC2  
CLKT2  
CLK_INT  
CLK_INC  
AGND  
AVDD  
CLKT3  
CLKC3  
CLKT0  
GND  
CLKC0  
GND  
NB  
CLKC5  
GND  
NB  
CLKT5  
GND  
GND  
OS  
CLKT6  
CLKC6  
CLKC7  
CLKT7  
GND  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
GND  
VDDQ  
NB  
NB  
VDDQ  
NB  
VDDQ  
NB  
NB  
VDDQ  
NB  
VDDQ  
OE  
VDDQ  
GND  
GND  
CLKC9  
FB_INT  
FB_INC  
FB_OUTC  
FB_OUTT  
CLKT8  
GND  
GND  
CLKT4  
GND  
CLKT9  
K
CLKC4  
CLKC8  
Block Diagram  
CLKT0  
CLKC0  
LD* or OE  
OE  
Powerdown  
Control and  
Test Logic  
CLKT1  
CLKC1  
LD*, OS or OE  
OS  
40  
31  
AVDD  
CLKT2  
CLKC2  
30  
1
VDDQ  
CLKC7  
CLKT7  
VDDQ  
FB_INT  
FB_INC  
FB_OUTC  
FB_OUTT  
VDDQ  
OE  
PLL bypass  
LD*  
CLKC2  
CLKT2  
CLK_INT  
CLK_INC  
VDDQ  
CLKT3  
CLKC3  
CLKT4  
CLKC4  
ICS97ULP877B  
CLKT5  
CLKC5  
AGND  
AVDD  
VDDQ  
CLK_INT  
CLKT6  
CLKC6  
CLK_INC  
10K-100k  
GND 10  
21  
OS  
CLKT7  
CLKC7  
PLL  
GND  
11  
20  
CLKT8  
CLKC8  
FB_INT  
FB_INC  
CLKT9  
CLKC9  
* The Logic Detect (LD) powers down the device when a  
logic low is applied to both CLK_INT and CLK_INC.  
40-Pin MLF  
FB_OUTT  
FB_OUTC  
0981B—03/15/05  

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